Atmel Xplained Pro Evaluation Kit ATSAMD20-XPRO ATSAMD20-XPRO Scheda Tecnica
Codici prodotto
ATSAMD20-XPRO
282
Atmel | SMART SAM D20 [DATASHEET]
Atmel-42129K–SAM-D20_datasheet–06/2014
21.5.2 Power Management
During reset, all PORT lines are configured as inputs with input buffers, output buffers and pull disabled.
If the PORT peripheral is shut down, the latches contained in the pad will retain their current configuration, such as the
output value and pull settings. However, the PORT configuration registers and input synchronizers will lose their
contents, and these will not be restored when PORT is powered up again. The user must, therefore, reconfigure the
PORT peripheral at power up to ensure it is in a well-defined state before use.
output value and pull settings. However, the PORT configuration registers and input synchronizers will lose their
contents, and these will not be restored when PORT is powered up again. The user must, therefore, reconfigure the
PORT peripheral at power up to ensure it is in a well-defined state before use.
The PORT will continue to operate in any sleep mode where the selected module source clock is running.
21.5.3 Clocks
The PORT bus clock (CLK_PORT_APB) can be enabled and disabled in the Power Manager, and the default state of
CLK_PORT_APB can be found in the Peripheral Clock Masking section in the
CLK_PORT_APB can be found in the Peripheral Clock Masking section in the
The PORT is fed by two different clocks: a CPU main clock, which allows the CPU to access the PORT through the low-
latency CPU local bus (IOBUS), and an APB clock, which is a divided clock of the CPU main clock and allows the CPU to
access the PORT registers through the high-speed matrix and the AHB/APB bridge.
latency CPU local bus (IOBUS), and an APB clock, which is a divided clock of the CPU main clock and allows the CPU to
access the PORT registers through the high-speed matrix and the AHB/APB bridge.
IOBUS accesses have priority over APB accesses. The latter must insert wait states in the event of concurrent PORT
accesses.
accesses.
The PORT input synchronizers use the CPU main clock so that the resynchronization delay is minimized with respect to
the APB clock.
the APB clock.
21.5.4 DMA
Not applicable.
21.5.5 Interrupts
Not applicable.
21.5.6 Events
Not applicable.
21.5.7 Debug Operation
When the CPU is halted in debug mode, the PORT continues normal operation. If the PORT is configured in a way that
requires it to be periodically serviced by the CPU through interrupts or similar, improper operation or data loss may result
during debugging.
requires it to be periodically serviced by the CPU through interrupts or similar, improper operation or data loss may result
during debugging.
21.5.8 Register Access Protection
All registers with write-access are optionally write-protected by the Peripheral Access Controller (PAC).
Write-protection is denoted by the Write-Protected property in the register description.
When the CPU is halted in debug mode, all write-protection is automatically disabled.
Write-protection does not apply for accesses through an external debugger. Refer to
21.5.9 Analog Connections
Analog functions are connected directly between the analog blocks and the I/O pads using analog buses. However,
selecting an analog peripheral function for a given pin will disable the corresponding digital features of the pad.
selecting an analog peripheral function for a given pin will disable the corresponding digital features of the pad.
21.5.10 CPU Local Bus
The CPU local bus (IOBUS) is an interface that connects the CPU directly to the PORT. It is a single-cycle bus interface,
and does not support wait states. It supports byte, half word and word sizes.
and does not support wait states. It supports byte, half word and word sizes.