Linear Technology LTC2171-14 14-Bit, 40Msps, 1.8V Quad Serial ADC, 5MHz DC1525A-E Scheda Tecnica
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DC1525A-E
3
dc1525af
DEMO MANUAL DC1525A
QUICK START PROCEDURE
CHANNEL 4
dc1525a F01
CHANNEL 3
CHANNEL 2
PARALLEL/SERIAL
CHANNEL 1
ANALOG INPUTS
TO PROVIDED
POWER SUPPLY
POWER SUPPLY
USE PROVIDED
USB CABLE
USB CABLE
3.5V
TO 6V
SINGLE-ENDED ENCODE CLOCK
USE PROVIDED DC1075
USE PROVIDED DC1075
Figure 1. DC1525A Setup
Analog Input Network
For optimal distortion and noise performance the RC
network on the analog inputs may need to be optimized
for different analog input frequencies. For input frequen-
cies above 140MHz, refer to the LTC2175 data sheet for a
proper input network. Other input networks may be more
appropriate for input frequencies less that 5MHz.
network on the analog inputs may need to be optimized
for different analog input frequencies. For input frequen-
cies above 140MHz, refer to the LTC2175 data sheet for a
proper input network. Other input networks may be more
appropriate for input frequencies less that 5MHz.
In almost all cases, filters will be required on both analog
input and encode clock to provide data sheet SNR.
input and encode clock to provide data sheet SNR.
The filters should be located close to the inputs to avoid
reflections from impedance discontinuities at the driven
end of a long transmission line. Most filters do not present
50Ω outside the passband. In some cases, 3dB to 10dB
pads may be required to obtain low distortion.
reflections from impedance discontinuities at the driven
end of a long transmission line. Most filters do not present
50Ω outside the passband. In some cases, 3dB to 10dB
pads may be required to obtain low distortion.
If your generator cannot deliver full-scale signals without
distortion, you may benefit from a medium power amplifier
based on a Gallium Arsenide Gain block prior to the final
filter. This is particularly true at higher frequencies where
IC based operational amplifiers may be unable to deliver
distortion, you may benefit from a medium power amplifier
based on a Gallium Arsenide Gain block prior to the final
filter. This is particularly true at higher frequencies where
IC based operational amplifiers may be unable to deliver
the combination of low noise figure and High IP3 point
required. A high order filter can be used prior to this final
amplifier, and a relatively lower Q filter used between the
amplifier and the demo circuit.
required. A high order filter can be used prior to this final
amplifier, and a relatively lower Q filter used between the
amplifier and the demo circuit.
Apply the analog input signal of interest to the SMA con-
nectors on the DC1525A demonstration circuit board
marked J3 AIN1, J4 AIN2, J6 AIN3, J7 AIN4. These inputs
correspond with channels 1 to 4 of the ADC respectively.
These inputs are capacitive coupled to Balun transform-
ers ETC1-1-13.
nectors on the DC1525A demonstration circuit board
marked J3 AIN1, J4 AIN2, J6 AIN3, J7 AIN4. These inputs
correspond with channels 1 to 4 of the ADC respectively.
These inputs are capacitive coupled to Balun transform-
ers ETC1-1-13.
Encode Clock
NOTE: Apply an encode clock to the SMA connector on
the DC1525A demonstration circuit board marked J11
CLK+. As a default the DC1525A is populated to have a
single-ended input.
the DC1525A demonstration circuit board marked J11
CLK+. As a default the DC1525A is populated to have a
single-ended input.
For the best noise performance, the ENCODE INPUT must
be driven with a very low jitter, square wave source. The
amplitude should be large, up to 3V
be driven with a very low jitter, square wave source. The
amplitude should be large, up to 3V
P-P
or 13dBm. When