STMicroelectronics 250W TRANSITION-MODE PFC PRE-REGULATOR WITH L6563S EVL6563S-250W EVL6563S-250W Scheda Tecnica

Doc ID 16849 Rev 2

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The measured output voltage at different line and static load conditions is shown in 

. As seen, the voltage is very stable over all the input voltage and output load 

range.

In the following images the waveforms relevant to the switch current at 100 Vac voltage 
mains are shown; in 

 and 

 it can be noted that the current peaks in the two 

MOSFETs in parallel are very close to each other, demonstrating the perfect current sharing 
between the two devices. The two MOSFETs in parallel allow the total thermal resistance 
junction-heat sink to decrease, therefore the same peak current can be managed using two 
smaller and cheaper MOSFETs instead of a bigger one. 

In 

, close to the zero crossing points of the sinewave, it is possible to note the 

action of the THD optimizer embedded in the L6563S. It is a circuit which minimizes the 
conduction dead-angle occurring at the AC input current near the zero-crossings of the line 
voltage (crossover distortion). In this way, the THD (total harmonic distortion) of the current 
is considerably reduced. A major cause of this distortion is the inability of the system to 
transfer energy effectively when the instantaneous line voltage is very low. This effect is 
magnified by the high frequency filter capacitor placed after the bridge rectifier, which 
retains some residual voltage causing the diodes of the bridge rectifier to be reverse-biased 
and the input current flow to temporarily stop. To overcome this issue the device forces the 
PFC pre-regulator to process more energy near the line voltage zero-crossings as 
compared to that commanded by the control loop. This results in both minimizing the time 
interval where energy transfer is lacking and fully discharging the high-frequency filter 
capacitor after the bridge. Essentially, the circuit artificially increases the on-time of the 
power switch with a positive offset added to the output of the multiplier in the proximity of the 
line voltage zero-crossings. This offset is reduced as the instantaneous line voltage 
increases, so that it becomes negligible as the line voltage moves towards the top of the 
sinusoid. Furthermore, the offset is modulated by the voltage on the V

FF

 pin so as to have 

as little offset at low-line, where energy transfer at zero crossings is typically quite good, and 
a larger offset at high-line where the energy transfer gets worse.

To achieve maximum benefit from the THD optimizer circuit, the high-frequency filter 
capacitors after the bridge rectifier should be minimized, maintaining compatibility with EMI 

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