Intel III M 866 MHz BXM80530B866512 Scheda Tecnica
Codici prodotto
BXM80530B866512
Mobile Intel
®
Pentium
®
III Processor in BGA2 and Micro-PGA2 Packages at 1 GHz,
900 MHz, 850 MHz, 800 MHz, 750 MHz, 700 MHz, Low-voltage 750 MHz, Low-voltage 700 MHz,
Low-voltage 600 MHz, Ultra Low-voltage 600 MHz and Ultra Low-voltage 500 MHz
Low-voltage 600 MHz, Ultra Low-voltage 600 MHz and Ultra Low-voltage 500 MHz
20 Datasheet
283653-002
2.2.9
Operating System Implications of Low-power States
There are a number of architectural features of the mobile Pentium III processor that do not
function in the Quick Start or Sleep state as they do in the Stop Grant state. The time-stamp
counter and the performance monitor counters are not guaranteed to count in the Quick Start or
Sleep states. The local APIC timer and performance monitor counter interrupts should be disabled
before entering the Deep Sleep state or the resulting behavior will be unpredictable.
function in the Quick Start or Sleep state as they do in the Stop Grant state. The time-stamp
counter and the performance monitor counters are not guaranteed to count in the Quick Start or
Sleep states. The local APIC timer and performance monitor counter interrupts should be disabled
before entering the Deep Sleep state or the resulting behavior will be unpredictable.
2.2.10
Intel SpeedStep Technology
Some mobile Pentium III processors will be offered with Intel SpeedStep technology. The Intel
SpeedStep technology allows the processor switch between two core frequencies without having
to reset the processor or change the system bus frequency. The processor has two bus ratios
programmed into it instead of one and the GHI# signal controls which one is used. After reset, the
processor will start in the lower of its two core frequencies, the “Battery Optimized” mode. An
operating mode transition to the high core frequency can be made by putting the processor into the
Deep Sleep state, raising the core voltage, setting GHI# low, and returning to the Normal state.
This puts the processor into the “Maximum performance” mode. A transitioning back to the low-
core frequency can be made by reversing these steps.
SpeedStep technology allows the processor switch between two core frequencies without having
to reset the processor or change the system bus frequency. The processor has two bus ratios
programmed into it instead of one and the GHI# signal controls which one is used. After reset, the
processor will start in the lower of its two core frequencies, the “Battery Optimized” mode. An
operating mode transition to the high core frequency can be made by putting the processor into the
Deep Sleep state, raising the core voltage, setting GHI# low, and returning to the Normal state.
This puts the processor into the “Maximum performance” mode. A transitioning back to the low-
core frequency can be made by reversing these steps.
2.3 GTL+
Signals
The mobile Pentium III processor system bus signals use a variation of the low-voltage swing GTL
signaling technology. The mobile Pentium III processor system bus specification is similar to the
Pentium II processor system bus specification, which is a version of GTL with enhanced noise
margins and less ringing.
signaling technology. The mobile Pentium III processor system bus specification is similar to the
Pentium II processor system bus specification, which is a version of GTL with enhanced noise
margins and less ringing.
The GTL+ system bus depends on incident wave switching and uses flight time for timing
calculations of the GTL+ signals, as opposed to capacitive derating. Analog signal simulation of
the system bus including trace lengths is highly recommended. Contact your field sales
representative to receive the IBIS models for the mobile Pentium III processor.
calculations of the GTL+ signals, as opposed to capacitive derating. Analog signal simulation of
the system bus including trace lengths is highly recommended. Contact your field sales
representative to receive the IBIS models for the mobile Pentium III processor.
The GTL+ system bus of the Pentium II processor was designed to support high-speed data
transfers with multiple loads on a long bus that behaves like a transmission line. However, in
mobile systems the system bus only has two loads (the processor and the chipset) and the bus
traces are short. It is possible to change the layout and termination of the system bus to take
advantage of the mobile environment using the same GTL+ I/O buffers. In mobile systems the
GTL+ system bus is terminated at one end only. This termination is provided on the processor
core (except for the RESET# signal). Refer to the Mobile Pentium
transfers with multiple loads on a long bus that behaves like a transmission line. However, in
mobile systems the system bus only has two loads (the processor and the chipset) and the bus
traces are short. It is possible to change the layout and termination of the system bus to take
advantage of the mobile environment using the same GTL+ I/O buffers. In mobile systems the
GTL+ system bus is terminated at one end only. This termination is provided on the processor
core (except for the RESET# signal). Refer to the Mobile Pentium
®
III Processor GTL+ System
Bus Layout Guideline for details on laying out the GTL+ system bus.
2.4
Mobile Pentium III Processor CPUID
The CPUID instruction does not distinguish between the Pentium
III
processor and the mobile
Pentium
III
processor. After a power-on RESET or when the CPUID version information is
Table 4. After the L2 cache is initialized, the CPUID cache/TLB descriptors will be the values
shown in Table 5.
shown in Table 5.