Intel III M 866 MHz BXM80530B866512 Scheda Tecnica
Codici prodotto
BXM80530B866512
Mobile Intel
®
Pentium
®
III Processor in BGA2 and Micro-PGA2 Packages at 1 GHz,
900 MHz, 850 MHz, 800 MHz, 750 MHz, 700 MHz, Low-voltage 750 MHz, Low-voltage 700 MHz,
Low-voltage 600 MHz, Ultra Low-voltage 600 MHz and Ultra Low-voltage 500 MHz
Low-voltage 600 MHz, Ultra Low-voltage 600 MHz and Ultra Low-voltage 500 MHz
22 Datasheet
283653-002
3. Electrical
Specifications
3.1
Processor System Signals
Table 6 lists the processor system signals by type. All GTL+ signals are synchronous with the
BCLK signal. All TAP signals are synchronous with the TCK signal except TRST#. All CMOS
input signals can be applied asynchronously.
BCLK signal. All TAP signals are synchronous with the TCK signal except TRST#. All CMOS
input signals can be applied asynchronously.
Table 6. System Signal Groups
Group Name
Signals
GTL+ Input
BPRI#, DEFER#, RESET#, RS[2:0]#, RSP#, TRDY#
GTL+ Output
PRDY#
GTL+ I/O
A[35:3]#, ADS#, AERR#, AP[1:0]#, BERR#, BINIT#, BNR#, BP[3:2]#,
BPM[1:0]#, BREQ0#, D[63:0]#, DBSY#, DEP[7:0]#, DRDY#, HIT#, HITM#,
LOCK#, REQ[4:0]#, RP#
BPM[1:0]#, BREQ0#, D[63:0]#, DBSY#, DEP[7:0]#, DRDY#, HIT#, HITM#,
LOCK#, REQ[4:0]#, RP#
1.5V CMOS Input
2
A20M#, FLUSH#, GHI#, IGNNE#, INIT#, LINT0/INTR, LINT1/NMI, PREQ#,
SLP#, SMI#, STPCLK#
SLP#, SMI#, STPCLK#
2.5V CMOS Input
1, 3
PWRGOOD
1.5V Open Drain Output
2
FERR#,
IERR#
3.3V CMOS Input
4
BSEL[1:0]
Clock
3
BCLK
APIC Clock
3
PICCLK
APIC I/O
2
PICD[1:0]
Thermal Diode
THERMDA, THERMDC
TAP Input
2
TCK, TDI, TMS, TRST#
TAP Output
2
TDO
Power/Other
5
CLKREF, CMOSREF, EDGECTRLP, NC, PLL1, PLL2, RSVD, RTTIMPEDP,
TESTHI, TESTLO[2:1], V
TESTHI, TESTLO[2:1], V
CC
, V
CCT
, VID[4:0], V
REF
, V
SS
NOTES:
1.
See Section 8.1 for information on the PWRGOOD signal.
2.
These signals are tolerant to 1.5V only. See Table 7 for the recommended pull-up resistor.
3.
These signals are tolerant to 2.5V only. See Table 7 for the recommended pull-up resistor.
4.
These signals are tolerant to 3.3V only. See Table 7 for the recommended pull-up resistor.
5.
V
CC
is the power supply for the core logic.
PLL1 and PLL2 are the power supply for the PLL analog section.
V
V
CCT
is the power supply for the system bus buffers.
V
REF
is the voltage reference for the GTL+ input buffers.
V
SS
is system ground.
The CMOS, APIC, and TAP inputs can be driven from ground to 1.5V. BCLK, PICCLK, and
PWRGOOD can be driven from ground to 2.5V. The APIC data and TAP outputs are Open-drain
and should be pulled up to 1.5V using resistors with the values shown in Table 7. If Open-drain
drivers are used for input signals, then they should also be pulled up to the appropriate voltage
using resistors with the values shown in Table 7.
PWRGOOD can be driven from ground to 2.5V. The APIC data and TAP outputs are Open-drain
and should be pulled up to 1.5V using resistors with the values shown in Table 7. If Open-drain
drivers are used for input signals, then they should also be pulled up to the appropriate voltage
using resistors with the values shown in Table 7.