Intel III M 866 MHz BXM80530B866512 Scheda Tecnica

 

 Mobile Intel

® 

Pentium

®

 III Processor in BGA2 and Micro-PGA2 Packages at 1 GHz,  

900 MHz, 850 MHz, 800 MHz, 750 MHz, 700 MHz, Low-voltage 750 MHz, Low-voltage  

700 MHz, Low-voltage 600 MHz, Ultra Low-voltage 600 MHz and Ultra Low-voltage 500 MHz 

283653-002 Datasheet 

25 

The CMOS input signals are allowed to be in either the logic high or low state when the processor 
is in a low-power state. In the Auto Halt and Stop Grant states these signals are allowed to toggle.  

These input buffers have no internal pull-up or pull-down resistors and system logic can use 
CMOS or Open-drain drivers to drive them. 

The Open-drain output signals have open drain drivers and external pull-up resistors are required. 
One of the two output signals (IERR#) is a catastrophic error indicator and is tri-stated (and 
pulled-up) when the processor is functioning normally. The FERR# output can be either tri-stated 
or driven to V

SS

 when the processor is in a low-power state depending on the condition of the 

floating point unit. Since this signal is a DC current path when it is driven to V

SS

, Intel 

recommends that the software clears or masks any floating-point error condition before putting the 
processor into the Deep Sleep state. 

The system bus clock (BCLK) must be driven in all of the low-power states except the Deep Sleep 
state. The APIC clock (PICCLK) must be driven whenever BCLK is driven unless the APIC is 
hardware disabled or the processor is in the Sleep state. Otherwise, it is permitted to turn off 
PICCLK by holding it at V

SS

. The system bus clock should be held at V

SS

 when it is stopped in the 

Deep Sleep state. 

In the Auto Halt and Stop Grant states the APIC bus data signals (PICD[1:0]) may toggle due to 
APIC bus messages. These signals are required to be tri-stated and pulled-up when the processor 
is in the Quick Start, Sleep, or Deep Sleep states unless the APIC is hardware disabled.  

The amount of bulk decoupling required on the V

CC

 and V

CCT

 planes to meet the voltage tolerance 

requirements for the mobile Pentium III processor are a strong function of the power supply 
design.  Contact your Intel Field Sales Representative for tools to help determine how much bulk 
decoupling is required.  

For a processor with maximum performance mode at 900 MHz or 1 GHz, the transient de-
coupling recommendations are based on motherboard bulk decoupling, maximum Equivalent 
Series Resistance (ESR) equal to 3.5m

Ω

, and the implementation of voltage positioning between 

1.725V at light load and 1.660V at maximum load to reduce decoupling capacitor requirements.  
Actual implementations will be dependent on power supply design. 

For a processor with maximum performance mode at 700 MHz and above, the following 
decoupling is recommended. The processor core power plane (V

CC

) should have fifteen 0.68 

µ

F 

0603 ceramic capacitors (using X7R dielectric for thermal reasons) placed directly under the 
package using two vias for power and two vias for ground to reduce the trace inductance. Also to 
minimize inductance, traces to those vias should be 22mils (in width) from the capacitor pads to 
match the via-pad size (assuming 22-mil pad size). Twenty-four 2.2 

µ

F 0805, X5R mid frequency 

decoupling capacitors should be placed around the die as close to the die as flex solution allows.