Intel III M 866 MHz BXM80530B866512 Scheda Tecnica
Codici prodotto
BXM80530B866512
Mobile Intel
®
Pentium
®
III Processor in BGA2 and Micro-PGA2 Packages at 1 GHz,
900 MHz, 850 MHz, 800 MHz, 750 MHz, 700 MHz, Low-voltage 750 MHz, Low-voltage 700 MHz,
Low-voltage 600 MHz, Ultra Low-voltage 600 MHz and Ultra Low-voltage 500 MHz
Low-voltage 600 MHz, Ultra Low-voltage 600 MHz and Ultra Low-voltage 500 MHz
26 Datasheet
283653-002
The system bus buffer power plane (V
CCT
) should have twenty 0.1-
µ
F high frequency decoupling
capacitors around the die.
For a processor with maximum performance mode at 650 MHz and below, the following
decoupling is recommended. The processor core power plan (V
decoupling is recommended. The processor core power plan (V
CC
) should have twelve 0.1-
µ
F high
frequency decoupling capacitors placed underneath the die and twenty-seven 0.1-
µ
F mid
frequency decoupling capacitors placed around the die as close to the die (< 0.8” away) as flex
solution allows. The system bus buffer power plane (V
solution allows. The system bus buffer power plane (V
CCT
) should have fifteen 0.1-
µ
F high
frequency decoupling capacitors no further than 0.25 inches away from the V
CCT
vias (balls).
3.2.2 Voltage
Planes
All V
CC
and V
SS
pins/balls must be connected to the appropriate voltage plane. All V
CCT
and V
REF
pins/balls must be connected to the appropriate traces on the system electronics. In addition to the
main V
main V
CC
, V
CCT
, and V
SS
power supply signals, PLL1 and PLL2 provide analog decoupling to the
PLL section. PLL1 and PLL2 should be connected according to Figure 5. Do not connect PLL2
directly to V
directly to V
SS
. Appendix A contains the RLC filter specification.
Figure 5. PLL RLC Filter
PLL1
PLL2
V
CCT
V0027-01
L1
C1
R1
3.3
System Bus Clock and Processor Clocking
The 2.5-V BCLK clock input directly controls the operating speed of the system bus interface. All
system bus timing parameters are specified with respect to the rising edge of the BCLK input. The
mobile Pentium III processor core frequency is a multiple of the BCLK frequency. The processor
core frequency is configured during manufacturing. The configured bus ratio is visible to software
in the Power-on configuration register, see Section 7.2 for details.
system bus timing parameters are specified with respect to the rising edge of the BCLK input. The
mobile Pentium III processor core frequency is a multiple of the BCLK frequency. The processor
core frequency is configured during manufacturing. The configured bus ratio is visible to software
in the Power-on configuration register, see Section 7.2 for details.
Multiplying the bus clock frequency is necessary to increase performance while allowing for
easier distribution of signals within the system. Clock multiplication within the processor is
provided by the internal Phase Lock Loop (PLL), which requires a constant frequency BCLK
input. During Reset or on exit from the Deep Sleep state, the PLL requires some amount of time to
acquire the phase of BCLK. This time is called the PLL lock latency, which is specified in
Section 3.7, AC timing parameters T18 and T47.
easier distribution of signals within the system. Clock multiplication within the processor is
provided by the internal Phase Lock Loop (PLL), which requires a constant frequency BCLK
input. During Reset or on exit from the Deep Sleep state, the PLL requires some amount of time to
acquire the phase of BCLK. This time is called the PLL lock latency, which is specified in
Section 3.7, AC timing parameters T18 and T47.
3.4
Intel SpeedStep Technology
The mobile Pentium III processor featuring Intel SpeedStep technology is specified to operate in
either of two modes, the “Maximum Performance Mode” or the “Battery Optimized Mode”. Each
either of two modes, the “Maximum Performance Mode” or the “Battery Optimized Mode”. Each