Intel 4 HT 631 80552PG0802M2M Scheda Tecnica

Datasheet

19

 

VTT_OUT_LEFT 
and 
VTT_OUT_RIGHT 
I

CC

DC Current that may be drawn from 
VTT_OUT_LEFT and VTT_OUT_RIGHT per 
pin

—

—

580

mA

I

TT

Steady-state FSB termination current

—

—

3.5

A

15, 16

I

TT_P

OWER

-

UP

Power-up FSB termination current

—

—

4.5

A

, 17

I

CC_VCCA

I

CC

 for PLL lands

—

—

35

mA

I

CC_VCCIOPLL

I

CC

 for I/O PLL land

—

—

26

mA

I

CC_GTLREF

I

CC

 for GTLREF

—

—

200

µA

1. Unless otherwise noted, all specifications in this table are based on estimates and simulations or empirical data. These 

specifications will be updated with characterized data from silicon measurements at a later date.

2. Adherence to the voltage specifications for the processor are required to ensure reliable processor operation.

3. Each processor is programmed with a maximum valid voltage identification value (VID) that is set at manufacturing and can 

not be altered. Individual maximum VID values are calibrated during manufacturing such that two processors at the same 

frequency may have different settings within the VID range. Note that this differs from the VID employed by the processor 

during a power management event (Thermal Monitor 2, Enhanced Intel SpeedStep technology, or Enhanced HALT State). 

4.

These voltages are targets only. A variable voltage source should exist on systems in the event that a different 

voltage is required. See 

 and 

 for more information.

5. The voltage specification requirements are measured across VCC_SENSE and VSS_SENSE lands at the socket with a 100 MHz 

bandwidth oscilloscope, 1.5 pF maximum probe capacitance, and 1 M

Ω minimum impedance. The maximum length of ground 

wire on the probe should be less than 5 mm. Ensure external noise from the system is not coupled into the oscilloscope probe.

6.

Refer to 

 and 

 for the minimum, typical, and maximum V

CC

 allowed for a given current. The 

processor should not be subjected to any V

CC

 and I

CC

 combination wherein V

CC

 exceeds V

CC_MAX

 for a given 

current.

7. I

CC_MAX

 is specified at V

CC_MAX

.

8. The current specified is also for AutoHALT State.

9. I

CC

 Stop-Grant is specified at V

CC_MAX

.

10.I

SGNT

 and I

ENHANCED_AUTO_HALT

 are specified at V

CC_TYP

 and TC = 50 °C.

11.These parameters are based on design characterization and are not tested. 

12.The maximum instantaneous current the processor will draw while the thermal control circuit is active (as indicated by the 

assertion of PROCHOT#) is the same as the maximum I

CC

 for the processor.

13.V

TT

 must be provided via a separate voltage source and not be connected to V

CC

. This specification is measured at the land.

14.Baseboard bandwidth is limited to 20 MHz.

15.

This is maximum total current drawn from V

TT

 plane by only the processor. This specification does not include 

the current coming from R

TT

 (through the signal line). Refer to the 

 to determine the total I

TT

 drawn by the system. 

16.This is a steady-state I

TT

 current specification, which is applicable when both V

TT

 and V

CC

 are high.

17.This is a power-up peak current specification that is applicable when V

TT

 is high and V

CC

 is low.