Intel E3-1105C AV8062701048800 Scheda Tecnica
Codici prodotto
AV8062701048800
Electrical Specifications
Intel
®
Xeon
®
and Intel
®
Core™ Processors For Communications Infrastructure
Datasheet - Volume 1 of 2
May 2012
108
Document Number: 327405
-
001
9.11.3
Miscellaneous AC Specifications
9.11.4
TAP Signal Group AC Specifications
Table 9-22. Miscellaneous AC Specifications
T# Parameter
Min
Max
Unit
Figure
Notes
T1: Asynchronous GTL input pulse width
8
-
BCLKs
1,2,3
T4: PROCHOT# pulse width
500
-
μs
1,2,3
T5: THERMTRIP# assertion until V
CC
removed
-
500
ms
1,2,3
Notes:
1.
Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2.
All AC timing for the Asynchronous GTL signals are referenced to the BCLK rising edge at Crossing Voltage (V
CROSS
).
SM_DRAMPWROK are referenced to the BCLK rising edge at 0.5 * V
TT
.
3.
These signals may be driven asynchronously.
Table 9-23. TAP Signal Group AC Specifications
T# Parameter
Min
Max
Unit
Figure
Notes
T14: TCK Period
15
ns
1,2,3,4
T15: TDI, TMS Setup Time
6.5
ns
1,2,3,4
T16: TDI, TMS Hold Time
6.5
ns
1,2,3,4
T17: TDO Clock to Output Delay
0
5
ns
1,2,3,4
T18: TRST# Assert Time
2
T
TCK
1,2,3,4,5
Notes:
1.
Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2.
Not 100% tested. Specified by design characterization.
3.
It is recommended that TMS be asserted while TRST# is being deasserted.
4.
Referenced to the rising edge of TCK.
5.
TRST# is synchronized to TCK and asserted for 5 TCK periods while TMS is asserted.