Scheda Tecnica (AV8062701048800)SommarioIntel® Xeon® and Intel® Core™ Processors For Communications Infrastructure1Legal Lines and Disclaimers2Revision History3Contents4Figures6Tables71.0 Introduction111.1 Purpose / Scope / Audience111.2 Related Documents111.3 Terminology132.0 Product Overview152.1 Product Features172.2 Processor Details172.3 Supported Technologies172.4 Interface Features172.4.1 System Memory Support172.4.2 PCI Express*182.4.3 Direct Media Interface (DMI)202.4.4 Platform Environment Control Interface (PECI)202.5 Power Management Support212.5.1 Processor Core212.5.2 System212.5.3 Memory Controller212.5.4 PCI Express*212.5.5 DMI212.6 Thermal Management Support212.7 Package212.8 Testability213.0 Interfaces233.1 System Memory Interface233.1.1 System Memory Configurations Supported233.1.1.1 UDIMM Configurations243.1.1.2 SO-DIMM Configurations253.1.1.3 Memory Down Configurations263.1.2 System Memory Timing Support263.1.3 System Memory Organization Modes273.1.3.1 Single-Channel Mode273.1.3.2 Dual-Channel Mode - Intel® Flex Memory Technology Mode273.1.4 Rules for Populating Memory Slots283.1.5 Technology Enhancements of Intel® Fast Memory Access (Intel® FMA)283.1.5.1 Just-in-Time Command Scheduling293.1.5.2 Command Overlap293.1.5.3 Out-of-Order Scheduling293.1.5.4 Memory Type Range Registers (MTRRs) Enhancement293.1.6 Data Scrambling293.1.7 DRAM Clock Generation293.2 PCI Express* Interface293.2.1 PCI Express* Architecture303.2.1.1 Transaction Layer313.2.1.2 Data Link Layer313.2.1.3 Physical Layer313.2.2 PCI Express* Configuration Mechanism323.2.3 PCI Express* Port Bifurcation323.2.4 PCI Express* Lanes Connection343.2.5 Configuring PCIe* Lanes353.2.6 Lane Reversal on PCIe* Interface363.3 Direct Media Interface363.3.1 DMI Error Flow363.3.2 DMI Link Down363.4 Platform Environment Control Interface (PECI)363.5 Interface Clocking373.5.1 Internal Clocking Requirements374.0 Technologies394.1 Intel® Virtualization Technology394.1.1 Intel® VT-x Objectives394.1.2 Intel® VT-x Features394.1.3 Intel® VT-d Objectives404.1.4 Intel® VT-d Features404.1.5 Intel® VT-d Features Not Supported414.2 Intel® Hyper-Threading Technology414.3 Intel® Advanced Vector Extensions (Intel® AVX)414.4 Intel® Advanced Encryption Standard New Instructions (Intel® AES-NI)424.4.1 PCLMULQDQ Instruction424.5 Intel® 64 Architecture x2APIC425.0 Processor SKUs455.1 Overview455.1.1 SKU Features456.0 Power Management476.1 ACPI States Supported486.1.1 System States486.1.2 Processor Core/Package Idle States486.1.3 Integrated Memory Controller States486.1.4 PCIe* Link States496.1.5 DMI States496.1.6 Interface State Combinations496.2 Processor Core Power Management496.2.1 Enhanced Intel SpeedStep® Technology506.2.2 Low-Power Idle States506.2.3 Requesting Low-Power Idle States516.2.4 Core C-states526.2.4.1 Core C0 State526.2.4.2 Core C1/C1E State526.2.4.3 Core C3 State536.2.4.4 Core C6 State536.2.4.5 Core C7 State536.2.4.6 C-State Auto-Demotion536.2.5 Package C-States536.2.5.1 Package C0556.2.5.2 Package C1/C1E556.2.5.3 Package C3 State566.2.5.4 Package C6 State566.2.5.5 Package C7 State566.2.5.6 Dynamic L3 Cache Sizing566.3 IMC Power Management576.3.1 Disabling Unused System Memory Outputs576.3.2 DRAM Power Management and Initialization576.3.2.1 Initialization Role of CKE596.3.2.2 Dynamic Power Down Operation596.3.2.3 DRAM I/O Power Management596.4 PCIe* Power Management596.5 DMI Power Management596.6 Thermal Power Management597.0 Thermal Management617.1 Thermal Design Power (TDP) and Junction Temperature (TJ)617.2 Thermal and Power Specifications617.3 Thermal Management Features637.3.1 Processor Package Thermal Features637.3.1.1 Adaptive Thermal Monitor637.3.1.2 Digital Thermal Sensor657.3.1.3 PROCHOT# Signal667.3.2 Processor Core Specific Thermal Features687.3.2.1 On-Demand Mode687.3.3 Memory Controller Specific Thermal Features687.3.3.1 Programmable Trip Points687.3.4 Platform Environment Control Interface (PECI)687.3.4.1 Fan Speed Control with Digital Thermal Sensor698.0 Signal Description718.1 System Memory Interface718.2 Memory Reference and Compensation748.3 Reset and Miscellaneous Signals748.4 PCI Express* Based Interface Signals758.5 DMI758.6 PLL Signals768.7 TAP Signals768.8 Error and Thermal Protection778.9 Power Sequencing788.10 Processor Power and Ground Signals788.11 Sense Pins798.12 Future Compatibility798.13 Processor Internal Pull Up/Pull Down799.0 Electrical Specifications819.1 Power and Ground Pins819.2 Decoupling Guidelines819.2.1 Voltage Rail Decoupling819.3 Processor Clocking (BCLK, BCLK#)829.3.1 PLL Power Supply829.4 Serial Voltage Identification (SVID)829.5 System Agent (SA) Vcc VID899.6 Reserved or Unused Signals909.7 Signal Groups909.8 Test Access Port (TAP) Connection929.9 Storage Conditions Specifications929.10 DC Specifications939.10.1 Voltage and Current Specifications949.10.2 Platform Environmental Control Interface DC Specifications999.10.2.1 PECI Bus Architecture999.10.2.2 PECI DC Characteristics1009.10.2.3 Input Device Hysteresis1019.11 AC Specifications1019.11.1 DDR3 AC Specifications1039.11.2 PCI Express* AC Specification1079.11.3 Miscellaneous AC Specifications1089.11.4 TAP Signal Group AC Specifications1089.11.5 SVID Signal Group AC Specifications1099.12 Processor AC Timing Waveforms1099.13 Signal Quality1149.13.1 Input Reference Clock Signal Quality Specifications1159.13.2 DDR3 Signal Quality Specifications1159.13.3 I/O Signal Quality Specifications1159.14 Overshoot/Undershoot Guidelines1159.14.1 VCC Overshoot Specification1159.14.2 Overshoot/Undershoot Magnitude1169.14.3 Overshoot/Undershoot Pulse Duration11610.0 Processor Ball and Package Information11910.1 Processor Ball Assignments11910.2 Package Mechanical Information14611.0 Processor Configuration Registers15111.1 ERRSTS - Error Status15211.2 ERRCMD - Error Command15311.3 SMICMD - SMI Command15411.4 SCICMD - SCI Command15511.5 ECCERRLOG0_C0 - ECC Error Log 015511.6 ECCERRLOG1_C0 - ECC Error Log 115611.7 ECCERRLOG0_C1 - ECC Error Log 015711.8 ECCERRLOG1_C1 - ECC Error Log 115811.9 MAD_DIMM_CH0 - Address Decode Channel 015811.10 MAD_DIMM_CH1 - Address Decode Channel 116011.11 Error Detection and Correction161Dimensioni: 2,87 MBPagine: 164Language: EnglishApri il manuale
