Intel E3-1105C AV8062701048800 Scheda Tecnica

Intel

®

 Xeon

®

 and Intel

®

 Core™ Processors For Communications Infrastructure

May 2012

Datasheet - Volume 1 of 2

Document Number: 327405

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001

19

— Four single-lane PCI Express* ports intended for I/O via the PCH

• PCI Express* 1 x16 port is mapped to PCI Device 1.

— One 16-lane/Two 8-lane/One 8-lane and Two 4-lane PCI Express* port

• PCI Express* 1 x4 port is mapped to PCI Device 6.
• The port may negotiate down to narrower widths.

— Support for x16/x8/x4/x1 widths for a single PCI Express* mode.

• 2.5 GT/s and 5.0 GT/s PCI Express* frequencies are supported.
• Gen1 Raw bit-rate on the data pins of 2.5 Gb/s, resulting in a real bandwidth per 

pair of 250 MB/s given the 8b/10b encoding used to transmit data across this 

interface. This also does not account for packet overhead and link maintenance.

• Maximum theoretical bandwidth on interface of 4 GB/s in each direction 

simultaneously, for an aggregate of 8 GB/s when x16 Gen 1.

• Gen2 Raw bit-rate on the data pins of 5.0 Gb/s, resulting in a real bandwidth per 

pair of 500 MB/s given the 8b/10b encoding used to transmit data across this 

interface. This also does not account for packet overhead and link maintenance.

• Maximum theoretical bandwidth on interface of 8 GB/s in each direction 

simultaneously, for an aggregate of 8 GB/s when x16 Gen 2.

• Hierarchical PCI-compliant configuration mechanism for downstream devices.
• Traditional PCI style traffic (asynchronous snooped, PCI ordering).
• PCI Express* extended configuration space. The first 256 bytes of configuration 

space aliases directly to the PCI Compatibility configuration space. The remaining 

portion of the fixed 4-KB block of memory-mapped space above that (starting at 

100h) is known as extended configuration space.

• PCI Express* Enhanced Access Mechanism. Accessing the device configuration 

space in a flat memory mapped fashion.

• Automatic discovery, negotiation, and training of link out of reset.
• Traditional AGP style traffic (asynchronous non-snooped, PCI-X Relaxed ordering).
• Peer segment destination posted write traffic (no peer-to-peer read traffic) in 

Virtual Channel 0:

— DMI -> PCI Express* Port 1
— DMI -> PCI Express* Port 2
— PCI Express* Port 1 -> DMI
— PCI Express* Port 2 -> DMI

• 64-bit downstream address format, but the processor never generates an address 

above 64 GB (Bits 63:36 will always be zeros).

• 64-bit upstream address format, but the processor responds to upstream read 

transactions to addresses above 64 GB (addresses where any of Bits 63:36 are 

nonzero) with an Unsupported Request response. Upstream write transactions to 

addresses above 64 GB will be dropped.

• Re-issues configuration cycles that have been previously completed with the 

Configuration Retry status.

• PCI Express* reference clock is 100-MHz differential clock.
• Power Management Event (PME) functions.
• Dynamic width capability
• Message Signaled Interrupt (MSI and MSI-X) messages.
• Polarity inversion.