Intel E3-1105C AV8062701048800 Scheda Tecnica

Intel

®

 Xeon

®

 and Intel

®

 Core™ Processors For Communications Infrastructure

Datasheet - Volume 1 of 2

May 2012

68

Document Number: 327405

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001

The processor provides an auxiliary mechanism that allows system software to force 

the processor to reduce its power consumption via clock modulation. This mechanism is 

referred to as “On-Demand” mode and is distinct from Adaptive Thermal Monitor and 

bi-directional PROCHOT#. Processor platforms must not rely on software usage of this 

mechanism to limit the processor temperature. On-Demand Mode can be done via 

processor MSR or chipset I/O emulation.

On-Demand Mode may be used in conjunction with the Adaptive Thermal Monitor. 

However, if the system software tries to enable On-Demand mode at the same time the 

TCC is engaged, the factory configured duty cycle of the TCC overrides the duty cycle 

selected by the On-Demand mode. If the I/O based and MSR-based On-Demand modes 

are in conflict, the duty cycle selected by the I/O emulation-based On-Demand mode 

takes precedence over the MSR-based On-Demand Mode. 

If Bit 4 of the IA32_CLOCK_MODULATION MSR is set to a 1, the processor immediately 

reduces its power consumption via modulation of the internal core clock, independent 

of the processor temperature. The duty cycle of the clock modulation is programmable 

via Bits 3:1 of the same IA32_CLOCK_MODULATION MSR. In this mode, the duty cycle 

can be programmed in either 12.5% or 6.25% increments (discoverable via CPU ID). 

Thermal throttling using this method modulates each processor core’s clock 

independently. 

I/O emulation-based clock modulation provides legacy support for operating system 

software that initiates clock modulation through I/O writes to ACPI defined processor 

clock control registers on the chipset (PROC_CNT). Thermal throttling using this 

method modulates all processor cores simultaneously. 

The memory controller provides the ability to initiate memory throttling based upon 

memory temperature.  The memory temperature can be provided to the memory 

controller via PECI or can be estimated by the memory controller based upon memory 

activity.  The temperature trigger points are programmable by memory mapped IO 

registers. 

This memory controller provides programmable critical, hot and warm trip points. 

Crossing a critical trip point forces a system shutdown. Crossing a hot or warm trip 

point initiates throttling. The amount of memory throttle at each trip point is 

programmable.  

The Platform Environment Control Interface (PECI) is a one-wire interface that provides 

a communication channel between Intel processor and chipset components to external 

monitoring devices. The processor implements a PECI interface to allow communication 

of processor thermal information to other devices on the platform. The processor 

provides a digital thermal sensor (DTS) for fan speed control. The DTS is calibrated at 

the factory to provide a digital representation of relative processor temperature. 

Averaged DTS values are read via the PECI interface.