Intel E3-1105C AV8062701048800 Scheda Tecnica

Intel

®

 Xeon

®

 and Intel

®

 Core™ Processors For Communications Infrastructure

Datasheet - Volume 1 of 2

May 2012

76

Document Number: 327405

-

001

BCLK

BCLK#

Differential bus clock input to the processor and PCI 

Express*.

I

Diff Clk

BPM#[7:0]

Breakpoint and Performance Monitor Signals: 

Outputs from the processor that indicate the status 

of breakpoints and programmable counters used 

for monitoring processor performance.

I/O

CMOS

PRDY#

PRDY# is a processor output used by debug tools 

to determine processor debug readiness.

O

Asynchronous CMOS

PREQ#

PREQ# is used by debug tools to request debug 

operation of the processor.

I

Asynchronous CMOS

TCK

TCK (Test Clock): Provides the clock input for the 

processor Test Bus (also known as the Test Access 

Port). TCK must be driven low or allowed to float 

during power on Reset.

I

CMOS

TDI

TDI (Test Data In): Transfers serial test data into 

the processor. TDI provides the serial input needed 

for JTAG specification support.

I

CMOS

TDO

TDO (Test Data Out) transfers serial test data out 

of the processor. TDO provides the serial output 

needed for JTAG specification support.

O

Open Drain

TMS

TMS (Test Mode Select): A JTAG specification 

support signal used by debug tools.

I

CMOS

TRST#

TRST# (Test Reset) resets the Test Access Port 

(TAP) logic. TRST# must be driven low during 

power on Reset. 

I

CMOS