Intel E3815 FH8065301567411 Scheda Tecnica
Codici prodotto
FH8065301567411
Power Up and Reset Sequence
Intel
®
Atom™ Processor E3800 Product Family
104
Datasheet
5.
SUS rails are turned off only if entering SoC G3 state (SoC lets the board/PMIC power management
system know if this is ok - that there are no wake up events expected by the SoC). They can turn off at
the same time, or in reverse power up order, just like the Switched/CORE rails.
6.
VDD_VTT shows a range of times at which it can turn off. Any time within this range is fine.
7.
SLP_S3# can be active before or after DRAM_CORE_PWROK and PMC_CORE_PWROK, but
DRAM_CORE_PWROK should go low before memory power rails go low and PMC_CORE_PWROK should
go low before Switched/CORE rails go low.
8.
Measurement of delays is at the 10% voltage mark. Contact your Intel representative for additional
details.
9.
The V1P35S rail “VGA_V1P35_S3_F1” must be powered down as shown above. All other V1P35S/VSFR
([X]_V1P35_S3_F[x]) rails can either power down as shown, or power down before V3P3S.
7.3.2
S3/S4/S5 to S0 (Exit Sleep States)
Sleep states (S3-S5) are exited based on Wake events. The Wake events will force the
system to a full on state (S0), although some non-critical subsystems might still be
powered down and have to be brought back manually. For example, the hard disk may
be powered down during a sleep state, and have to be enabled via an I/O pin before it
can be used. Upon exit from software-entered Sleep states (i.e., those initiated via the
PM1_CNT.SLP_EN bit), the PM1_STS_EN.WAK_STS bit will be set.
system to a full on state (S0), although some non-critical subsystems might still be
powered down and have to be brought back manually. For example, the hard disk may
be powered down during a sleep state, and have to be enabled via an I/O pin before it
can be used. Upon exit from software-entered Sleep states (i.e., those initiated via the
PM1_CNT.SLP_EN bit), the PM1_STS_EN.WAK_STS bit will be set.
To enable Wake Events, the possible causes of wake events (and their restrictions) are
shown in
shown in
.
Table 60. S3/S4/S5 to S0 Cause of Wake Events (Sheet 1 of 2)
Cause
Type
How Enabled
RTC Alarm
1
Internal
Set PM1_STS_EN.RTC_EN register bit
PMC_PWRBTN#
(Power Button)
(Power Button)
External
Default enabled as Wake event
GPIO_S5[7:0]
1
External
GPE0a_EN register (after having gone to S5 via
PM1_CNT.SLP_EN, but not after a power failure.)
Note: GPIOs that are in the core well are not capable of
waking the system from sleep states where the core
well is not powered.
PM1_CNT.SLP_EN, but not after a power failure.)
Note: GPIOs that are in the core well are not capable of
waking the system from sleep states where the core
well is not powered.