Texas TMS320C645X Manuale Utente
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5.39
INTDSTn Interrupt Status Decode Registers (INTDSTn_DECODE)
SRIO Registers
There are eight of these registers.
Figure 95. INTDSTn Interrupt Status Decode Registers (INTDSTn_DECODE)
31-16
ISDR[31-16]
R-0x00
LEGEND: R = Read only; -n = value after reset
15-0
ISDR[15-0]
R-0x00
LEGEND: R = Read only; -n = value after reset
Table 69. INTDSTn Interrupt Status Decode Registers (INTDSTn_DECODE) Field Descriptions
Bit
Field
Value
Description
31-0
ISDRn
Interrupt sources that select a particular physical interrupt destination, are mapped to specific bits in
the decode register. The interrupt sources are mapped to an interrupt decode register, only if the
ICRR routes the interrupt source to the corresponding physical interrupt. The status decode bit is a
logical "OR" of multiple interrupt sources that are mapped to the same bit.
the decode register. The interrupt sources are mapped to an interrupt decode register, only if the
ICRR routes the interrupt source to the corresponding physical interrupt. The status decode bit is a
logical "OR" of multiple interrupt sources that are mapped to the same bit.
Serial RapidIO (SRIO)
140
SPRU976 – March 2006