Texas TMS320C645X Manuale Utente
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5.40
INTDSTn Interrupt Rate Control Registers (INTDSTn_RATE_CNTL)
SRIO Registers
There are eight of these registers.
Figure 96. INTDSTn Interrupt Rate Control Registers (INTDSTn_RATE_CNTL)
31-16
COUNT_DOWN_VALUE
RW-0x00
LEGEND: R = Read only; -n = value after reset
15-0
COUNT_DOWN_VALUE
RW-0x00
LEGEND: R = Read only; -n = value after reset
Table 70. INTDSTn Interrupt Rate Control Registers (INTDSTn_RATE_CNTL) Field Descriptions
Bit
Field
Value
Description
31-0
COUNT_DOWN_
The rate at which an interrupt can be generated is controllable for each physical interrupt
VALUE
destination. Rate control is implemented with a programmable down-counter. The counter reloads
and immediately starts down-counting each time the CPU writes these registers. Once the rate
control counter register is written, and the counter value reaches zero (note the CPU may write zero
immediately for a zero count), the interrupt pulse generation logic is allowed to fire a single pulse if
any bits in the corresponding ICSR register bits are set (or become set after the zero count is
reached).
and immediately starts down-counting each time the CPU writes these registers. Once the rate
control counter register is written, and the counter value reaches zero (note the CPU may write zero
immediately for a zero count), the interrupt pulse generation logic is allowed to fire a single pulse if
any bits in the corresponding ICSR register bits are set (or become set after the zero count is
reached).
SPRU976 – March 2006
Serial RapidIO (SRIO)
141