Lanner electronic FW-7650 Manuale Utente

3.5 Chipset Features Setup

DRAM Clock :

The chipset support synchronous and asynchronous mode between

the host clock and DIMM clock.

Host CLK (default)

DIMM clock equal to host clock

66MHz

DIMM clock equal to 66MHz

SDRAM Cycle Length : This item allows you to select the SDRAM cycle length. The

settings are 2 or 3.

CAS latency Time:

When synchronous DRAM is installed, the number of clock

cycles of CAS latency depends on the DRAM timing. Do not reset this field from the
default value specified by the system designer.

DRAM RAS# to CAS# Delay:

This field lets you insert a timing delay