Texas Instruments TMS320DM643x Manuale Utente
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5.4.6 PLL Controller Divider 2 Register (PLLDIV2)
5.4.7 PLL Controller Divider 3 Register (PLLDIV3)
PLL Controller Registers
The PLL controller divider 2 register (PLLDIV2) is shown in
and described in
Divider 2 controls divider for SYSCLK2.
Figure 5-8. PLL Controller Divider 2 Register (PLLDIV2)
31
16
Reserved
R-0
15
14
5
4
0
D2EN
Reserved
RATIO
R/W-1
R-0
R/W-2h or 9h
(1)
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
(1)
For PLLC1, RATIO defaults to 2h (PLL1 divide by 3); for PLLC2, RATIO defaults to 9h (PLL2 divide by 10).
Table 5-10. PLL Controller Divider 2 Register (PLLDIV2) Field Descriptions
Bit
Field
Value
Description
31-16
Reserved
0
Reserved
15
D2EN
Divider 2 enable.
0
Divider 2 is disabled.
1
Divider 2 is enabled.
14-5
Reserved
0
Reserved
4-0
RATIO
0-1Fh
Divider ratio. Divider value = RATIO + 1. For example, RATIO = 0 means divide by 1.
The PLL controller divider 3 register (PLLDIV3) is shown in
and described in
Divider 3 controls divider for SYSCLK3. PLLDIV3 is not used on PLLC2.
Figure 5-9. PLL Controller Divider 3 Register (PLLDIV3)
31
16
Reserved
R-0
15
14
5
4
0
D3EN
Reserved
RATIO
R/W-1
R-0
R/W-5h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 5-11. PLL Controller Divider 3 Register (PLLDIV3) Field Descriptions
Bit
Field
Value
Description
31-16
Reserved
0
Reserved
15
D3EN
Divider 3 enable.
0
Divider 3 is disabled.
1
Divider 3 is enabled.
14-5
Reserved
0
Reserved
4-0
RATIO
0-1Fh
Divider ratio. Divider value = RATIO + 1. For example, RATIO = 0 means divide by 1.
PLL Controller
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SPRU978E – March 2008