Manuali utente per Intel 80386

Sommario

• 32-bit Architectu re

  1
• High-performance Implementation

  1
• Virtual Memory Support

  1
• Configurable Protection

  1
• Extended Debugging Support

  1
• Object Code Compatibility

  1
• Summary

  1
• 2.1 Registers

  2
• 2.1.1 General Registers

  2
• 2.1.2 Flags and Instruction Pointer

  2
• 2.1.3 Numeric Coprocessor Registers

  2
• 2.2 Memory and Logical Addressing

  2
• 2.2.1 Segments

  2
• 2.2.2 Logical Addresses

  2
• 2.2.3 Segment and Descriptor Registers

  2
• 2.2.4 Addressing Modes

  2
• 2.3 Data Types and Instructions

  2
• 2.3.1 Principal Data Types

  2
• 2.3.2 Numeric Coprocessor Data Types

  2
• 2.3.3 Other Instructions

  2
• 2.3.3.1 Stack Instructions

  2
• 2.3.3.2 Control Transfer Instructions

  2
• 2.3.3.3 Miscellaneous Instructions

  2
• 3.1 System Registers

  3
• 3.2 Multitasking

  3
• 3.2.1 Task State Segment

  3
• 3.2.2 Task Switching

  3
• 3.3 Addressing

  3
• 3.3.1 Address Translation Overview

  3
• 3.3.2 Segments

  3
• 3.3.3 Pages

  3
• 3.3.4 Virtual Memory

  3
• 3.4 Protection

  3
• 3.4.1 Privilege

  3
• 3.4.2 Privileged Instructions

  3
• 3.4.3 Segment Protection

  3
• 3.4.4 Page Protection

  3
• 3.5 System Calls

  3
• 3.6 Interrupts and Exceptions

  3
• 3.6.1 Interrupt Descriptor Table

  3
• 3.6.2 Debug Exceptions and Registers

  3
• 3.7 Input/Output

  3
• 4.1 80286 Compatibility

  4
• 4.2 Real and Virtual 86 Modes

  4
• 5.1 Internal Design

  5
• 5.2 External Interface

  5
• 5.2.1 Clock

  5
• 5.2.2 Data and Address Buses

  5
• 5.2.3 Bus Cycle Definition

  5
• 5.2.4 Bus Cycle Control

  5
• 5.2.5 Dynamic Bus Sizing

  5
• 5.2.6 Processor Status and Control

  5
• 5.2.7 Coprocessor Control

  5
• 80386 High Performance Microprocessor with Integrated Memory Management

  1
• TABLE OF CONTENTS

  3
• Register Overview

  7
• Register Descriptions

  8
• Debug and Test Registers

  13
• 32-Bit Memory Addressing Modes

  17
• Data Types

  19
• 2.11.1 Self-Test

  27
• 2.12 Debugging Support

  27
• Global Descriptor Table

  36
• Local Descriptor Table

  36
• Descriptor Attribute Bits

  36
• System Descriptor Formats

  38
• LDT Descriptors (S = 0, TYPE = 2)

  39
• Protection Concepts

  45
• Selector Privilege (RPL)

  45
• Call Gates

  49
• Page Directory

  52
• Page Tables

  53
• Page Level Protection (R/W, U/S Bits)

  53
• Signal Description

  60
• Address Bus (BEO# through BE3#, A2 through A31)

  61
• Bus Cycle Definition Signals (W/R#, D/C#, MilO, LOCK#)

  62
• Address Status (ADS #)

  63
• Transfer Acknowledge (READY#)

  63
• Next Address Request (NA #)

  63
• Bus Size 16 (BS16#)

  63
• Bus Arbitration Signals

  64
• Bus Hold Request (HOLD)

  64
• Bus Hold Acknowledge (HLDA)

  64
• Coprocessor Busy (BUSY#)

  64
• Coprocessor Error (ERROR#)

  65
• Introduction

  65
• Maskable Interrupt Request (INTR)

  65
• Bus Transfer Mechanism

  66
• Dynamic Data Bus Sizing

  68
• Operand Alignment

  70
• Read and Write Cycles

  75
• Non-pipelined Address

  76
• 5.4.3.4 Pipe lined Address

  80
• Halt Indication Cycle

  87
• MECHANICAL DATA

  94
• ELECTRICAL DATA

  100
• Introduction

  100
• Power and Grounding

  100
• Power Decoupling Recommendations

  100
• Resistor Recommendations

  100
• Other Connection Recommendations

  100
• Maximum Ratings

  101
• D.C. Specifications

  101
• A.C. Specifications

  102
• A.C. Spec Definitions

  102
• A.C. Specification Tables

  103
• A.C. Test Loads

  105
• A.C. Timing Waveforms

  105
• Designing for ICE-386 Use

  108
• INSTRUCTION SET

  110
• Instruction Encoding and Clock Count Summary

  110
• Instruction Encoding Details

  125
• Overview

  125
• 32-Bit Extensions of the Instruction Set

  126
• Encoding of Instruction Fields

  126
• Encoding of the Operand Length (w) Field

  126
• Encoding of the General Register (reg) Field

  126
• Encoding of the Segment Register (sreg) Field

  127
• Encoding of Address Mode

  127
• Encoding of Operation Direction (d) Field

  131
• Encoding of Sign-extend (s) Field

  131
• Encoding of Conditional Test (tUn) Field

  131
• Encoding of Control or Debug or Test Register (eee) Field

  131