Manual Do Utilizadoríndice analítico32-bit Architectu re1High-performance Implementation1Virtual Memory Support1Configurable Protection1Extended Debugging Support1Object Code Compatibility1Summary12.1 Registers22.1.1 General Registers22.1.2 Flags and Instruction Pointer22.1.3 Numeric Coprocessor Registers22.2 Memory and Logical Addressing22.2.1 Segments22.2.2 Logical Addresses22.2.3 Segment and Descriptor Registers22.2.4 Addressing Modes22.3 Data Types and Instructions22.3.1 Principal Data Types22.3.2 Numeric Coprocessor Data Types22.3.3 Other Instructions22.3.3.1 Stack Instructions22.3.3.2 Control Transfer Instructions22.3.3.3 Miscellaneous Instructions23.1 System Registers33.2 Multitasking33.2.1 Task State Segment33.2.2 Task Switching33.3 Addressing33.3.1 Address Translation Overview33.3.2 Segments33.3.3 Pages33.3.4 Virtual Memory33.4 Protection33.4.1 Privilege33.4.2 Privileged Instructions33.4.3 Segment Protection33.4.4 Page Protection33.5 System Calls33.6 Interrupts and Exceptions33.6.1 Interrupt Descriptor Table33.6.2 Debug Exceptions and Registers33.7 Input/Output34.1 80286 Compatibility44.2 Real and Virtual 86 Modes45.1 Internal Design55.2 External Interface55.2.1 Clock55.2.2 Data and Address Buses55.2.3 Bus Cycle Definition55.2.4 Bus Cycle Control55.2.5 Dynamic Bus Sizing55.2.6 Processor Status and Control55.2.7 Coprocessor Control580386 High Performance Microprocessor with Integrated Memory Management1TABLE OF CONTENTS3Register Overview7Register Descriptions8Debug and Test Registers1332-Bit Memory Addressing Modes17Data Types192.11.1 Self-Test272.12 Debugging Support27Global Descriptor Table36Local Descriptor Table36Descriptor Attribute Bits36System Descriptor Formats38LDT Descriptors (S = 0, TYPE = 2)39Protection Concepts45Selector Privilege (RPL)45Call Gates49Page Directory52Page Tables53Page Level Protection (R/W, U/S Bits)53Signal Description60Address Bus (BEO# through BE3#, A2 through A31)61Bus Cycle Definition Signals (W/R#, D/C#, MilO, LOCK#)62Address Status (ADS #)63Transfer Acknowledge (READY#)63Next Address Request (NA #)63Bus Size 16 (BS16#)63Bus Arbitration Signals64Bus Hold Request (HOLD)64Bus Hold Acknowledge (HLDA)64Coprocessor Busy (BUSY#)64Coprocessor Error (ERROR#)65Introduction65Maskable Interrupt Request (INTR)65Bus Transfer Mechanism66Dynamic Data Bus Sizing68Operand Alignment70Read and Write Cycles75Non-pipelined Address765.4.3.4 Pipe lined Address80Halt Indication Cycle87MECHANICAL DATA94ELECTRICAL DATA100Introduction100Power and Grounding100Power Decoupling Recommendations100Resistor Recommendations100Other Connection Recommendations100Maximum Ratings101D.C. Specifications101A.C. Specifications102A.C. Spec Definitions102A.C. Specification Tables103A.C. Test Loads105A.C. Timing Waveforms105Designing for ICE-386 Use108INSTRUCTION SET110Instruction Encoding and Clock Count Summary110Instruction Encoding Details125Overview12532-Bit Extensions of the Instruction Set126Encoding of Instruction Fields126Encoding of the Operand Length (w) Field126Encoding of the General Register (reg) Field126Encoding of the Segment Register (sreg) Field127Encoding of Address Mode127Encoding of Operation Direction (d) Field131Encoding of Sign-extend (s) Field131Encoding of Conditional Test (tUn) Field131Encoding of Control or Debug or Test Register (eee) Field131Tamanho: 10 MBPáginas: 194Language: EnglishAbrir o manual