Manuali utente per Kane Industries C6713CPU

Sommario

• 1 PREFACE

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• Document Organization

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• Documentation Overview

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• Notational conventions

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• Trademarks

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• Revision History

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• 2 HARDWARE OVERVIEW

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• Block Diagram of the C6713CPU

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• Figure 1: Block diagram of the C6713CPU

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• Figure 2: Top side of the C6713CPU

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• Figure 3: Bottom side of the C6713CPU

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• 2.2 Connectors

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• 2.2.1 micro-line® Connectors

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• 2.2.2 JTAG Connector

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• 2.3 Interfaces and Hardware Components

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• 2.3.1 FPGA

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• 2.3.2 External Memory (on-board SDRAM)

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• Figure 4: FPGA connections overview

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• 2.3.3 Flash Memory

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• 2.3.4 PLD

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• 2.3.5 UART / RS-232 Interface

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• 2.3.6 Temperature Sensor

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• 2.3.7 Reset Generator and Watchdog

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• 2.3.8 External Flags (XF signals)

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• 2.3.9 Power Supply of the Board

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• 2.4 Status LED's

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• 2.4.1 User Programmable LED's (PLD)

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• 2.4.2 User Programmable LED (FPGA)

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• 2.5 DSP peripherals

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• 2.5.1 Multichannel Audio Serial Ports (McASP)

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• 2.5.2 External Memory Interface (EMIF)

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• 2.5.3 Inter Integrated Circuit (I2C) Interfaces

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• 2.5.4 General Purpose Input / Output Pins (GPIO)

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• 2.5.5 Multi-channel Buffered Serial Ports (McBSP)

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• 2.5.6 Timers

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• 2.5.7 Host Port Interface (HPI)

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• 2.5.8 Interrupts

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• 2.5.9 DMA

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• 3 MEMORY MAPS AND DESCRIPTION OF THE PLD REGISTERS

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• TMS320C6713 Memory Map

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• Table 1: Memory map of the processor

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• C6713CPU Address Map

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• Internal fast SRAM

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• DSP Peripherals

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• External SDRAM

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• Flash Memory

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• Table 2: Memory map of the C6713CPU

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• Endianness

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• Figure 5: Data representation in memory in little endian configuration

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• 3.8 EMIF Configuration

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• 3.8.1 Default EMIF configuration

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• Description of the PLD Board Registers

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• Table 3: default initialization values for the FPGA related CE space registers

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• Table 4: CE2 default configuration

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• Table 5: CE3 default configuration

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• 3.10 Description of the PLD Registers

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• 3.10.1 Hardware Configuration Register (HWCFG)

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• Table 6: PLD and UART registers of the C6713CPU

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• Table 7: PLD register quick reference

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• 3.10.2 FPGA Control Register (FCR)

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• 3.10.3 LED Control Register (LED)

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• 3.10.4 Module Control Register (MCR)

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• 3.10.5 I2C Bus Control Register (I2C)

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• 3.10.6 External Flag Register (XF)

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• 3.10.7 Watchdog Register (WDG)

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• 3.10.8 Version Register (VER)

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• Table 8: Version register encoding

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• 4 BOOT PROCESS AND DEFAULT SETUP OF THE C6713CPU

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• Table 9: Default clock and EMIF settings of the C6713CPU

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• 5 USING THE FLASH FILE SYSTEM

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• 6 DESCRIPTION OF THE MICRO-LINE® BOARD CONNECTORS

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• Location of the Connectors

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• Figure 6: Connector locations

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• Connector Overview

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• Pinout Tables of the micro-line® Connector

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• Table 10: Connector overview

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• Table 11: Pinout of the micro-line® connectors

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• Table 12: Pinout summary for the McBSP interfaces

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• Table 13: Pinout summary for the timers

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• Table 14: Pinout summary for the I2C interfaces

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• Table 15: Pinout summary and signal routing for the McASP interfaces

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• Pinout of the JTAG Connector

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• Table 16: Pinout of the JTAG connector

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• Figure 7: JTAG adapter for the C6713CPU

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• 6.5 Function of the micro-line® Connector Pins

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• 6.5.1 Connector A

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• 6.5.2 Connector B

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• 6.5.3 Connector BB

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• 6.5.4 Connector D

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• 6.5.5 Connector E

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• 7 ENVIRONMENT

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• Minimum Connections

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• Figure 8: Supplying the C6713CPU with power

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• Figure 9: Connecting the serial interface (RS-232) to a PC

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• 7.2 Changing the Board Configuration

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• 7.2.1 Location of modifiable components

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• Table 17: Factory default configuration summary

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• Figure 10: Location of configuration elements (top side)

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• 7.2.2 Configuring DSP Clock Speed

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• Configuring for HPI or McASP1 Usage

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• Configuring micro-line® Pin D30 Termination

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• Configuring for I2C interface #0 Operation

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• Figure 11: Location of configuration elements (bottom side)

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• Configuring CLKS1 / SCL1 Termination

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• Configuring FPGA I/O Behavior When FPGA is not Loaded

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• 7.3 Signal Levels and Loads

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• 7.3.1 Input Voltage Levels for non-FPGA Signals

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• 7.3.2 Output Voltage Levels for non-FPGA Signals

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• 7.3.3 Allowed Output Loads

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• Supply Voltage

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• Power Consumption

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• Reset Timing

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• Ambient Temperature

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• Ambient Humidity

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• Table 18: Voltage limits for the C6713CPU

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• Table 19: Power consumption of the C6713CPU

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• Table 20: Reset timing

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• Dimensions of the Board

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• Figure 12: Dimensions of the C6713CPU (in millimeters)

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• Figure 13: Complete micro-line® footprint

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• Spare micro-line® Connectors

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• Figure 14: C6713CPU connector pins

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• 8 LIST OF ABBREVIATIONS USED IN THIS DOCUMENT

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• 9 LITERATURE REFERENCES

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