Scheda TecnicaSommario1.0 Device Overview9FIGURE 1-1: dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 Block Diagram10TABLE 1-1: Pinout I/O Descriptions (Continued)112.0 Guidelines for Getting Started with 16-bit Digital Signal Controllers132.1 Basic Connection Requirements132.2 Decoupling Capacitors13FIGURE 2-1: Recommended Minimum connection142.3 CPU Logic Filter Capacitor Connection (Vcap)142.4 Master Clear (MCLR) Pin14FIGURE 2-2: Example of MCLR Pin Connections142.5 ICSP Pins152.6 External Oscillator Pins15FIGURE 2-3: Suggested Placement of the Oscillator Circuit152.7 Oscillator Value Conditions on Device Start-up162.8 Configuration of Analog and Digital Pins During ICSP Operations162.9 Unused I/Os163.0 CPU173.1 Data Addressing Overview173.2 DSP Engine Overview173.3 Special MCU Features18FIGURE 3-1: dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 CPU Core Block Diagram18FIGURE 3-2: dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 Programmer’s Model193.4 CPU Resources203.5 CPU Control Registers21Register 3-1: SR: CPU STATUS Register (Continued)21Register 3-2: CORCON: CORE Control Register233.6 Arithmetic Logic Unit (ALU)243.7 DSP Engine24TABLE 3-1: DSP Instructions Summary24FIGURE 3-3: DSP Engine Block Diagram254.0 Memory Organization294.1 Program Address Space29FIGURE 4-1: Program Memory Maps for dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 Devices29FIGURE 4-2: Program Memory Organization304.2 Data Address Space31FIGURE 4-3: Data Memory Map for dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 Devices with 2 Kb RAM324.3 Program Memory Resources334.4 Special Function Register Maps34TABLE 4-1: CPU Core Registers Map (Continued)34TABLE 4-2: Change Notification Register Map for dsPIC33FJ32MC20235TABLE 4-3: Change Notification Register Map for dsPIC33FJ32MC204 and dsPIC33FJ16MC30435TABLE 4-4: Interrupt Controller Register Map36TABLE 4-5: Timer Register Map37TABLE 4-6: Input Capture Register Map37TABLE 4-7: Output Compare Register Map37TABLE 4-8: 6-Output PWM1 Register Map38TABLE 4-9: 2-Output PWM2 Register Map38TABLE 4-10: QEI1 Register Map39TABLE 4-11: I2C1 Register Map39TABLE 4-12: UART1 Register Map39TABLE 4-13: SPI1 Register Map39TABLE 4-14: ADC1 Register Map for dsPIC33FJ32MC20240TABLE 4-15: ADC1 Register Map for dsPIC33FJ32MC204 and dsPIC33FJ16MC30441TABLE 4-16: PERIPHERAL pin select INPUT Register Map42TABLE 4-17: PERIPHERAL pin select outPUT Register Map for dsPIC33FJ32MC20242TABLE 4-18: pERIPHERAL pin select outPUT Register Map for dsPIC33FJ32MC204 AND dsPIC33FJ16MC30443TABLE 4-19: PORTA Register Map FOR dsPIC33FJ32MC20243TABLE 4-20: PORTA Register Map for dsPIC33FJ32MC204 AND dsPIC33FJ16MC30443TABLE 4-21: PORTB Register Map44TABLE 4-22: PORTC Register Map for dsPIC33FJ32MC204 AND dsPIC33FJ16MC30444TABLE 4-23: System Control Register Map44TABLE 4-24: NVM Register Map45TABLE 4-25: PMD Register Map45FIGURE 4-4: CALL Stack Frame464.5 Instruction Addressing Modes46TABLE 4-26: Fundamental Addressing Modes Supported474.6 Modulo Addressing48FIGURE 4-5: Modulo Addressing Operation Example484.7 Bit-Reversed Addressing49FIGURE 4-6: Bit-Reversed Address Example50TABLE 4-27: Bit-Reversed Address Sequence (16-Entry)504.8 Interfacing Program and Data Memory Spaces51TABLE 4-28: Program Space Address Construction51FIGURE 4-7: Data Access from Program Space Address Generation52FIGURE 4-8: Accessing Program Memory with Table Instructions53FIGURE 4-9: Program Space Visibility Operation545.0 Flash Program Memory555.1 Table Instructions and Flash Programming55FIGURE 5-1: Addressing for Table Registers555.2 RTSP Operation565.3 Programming Operations56EQUATION 5-1: programming time56EQUATION 5-2: Minimum Row Write Time56EQUATION 5-3: Maximum Row Write Time565.4 Flash Memory Resources565.5 Control Registers56Register 5-1: NVMCON: Flash Memory Control Register57Register 5-2: NVMKEY: NonVolatile Memory Key RegisteR58EXAMPLE 5-1: Erasing a Program Memory Page59EXAMPLE 5-2: Loading the Write Buffers60EXAMPLE 5-3: Initiating a Programming Sequence606.0 Resets61FIGURE 6-1: Reset System Block Diagram616.1 Resets Resources626.2 Reset Control Registers63Register 6-1: RCON: Reset Control Register(1) (Continued)636.3 System Reset65TABLE 6-1: Oscillator Parameters65FIGURE 6-2: System Reset Timing66TABLE 6-2: Oscillator Delay676.4 Power-on Reset (POR)676.4.1 Brown-out Reset (BOR) and Power-up timer (PWRT)67FIGURE 6-3: Brown-out Situations686.5 External Reset (EXTR)686.6 Software RESET Instruction (SWR)686.7 Watchdog Time-out Reset (WDTO)686.8 Trap Conflict Reset686.9 Configuration Mismatch Reset696.10 Illegal Condition Device Reset696.11 Using the RCON Status Bits69TABLE 6-3: Reset Flag Bit Operation697.0 Interrupt Controller717.1 Interrupt Vector Table717.2 Reset Sequence71FIGURE 7-1: dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 Interrupt Vector Table72TABLE 7-1: Interrupt Vectors73TABLE 7-2: Trap Vectors737.3 Interrupt Resources747.4 Interrupt Control and Status Registers74Register 7-1: SR: CPU STATUS Register(1)75Register 7-2: CORCON: CORE Control Register(1)75Register 7-3: INTCON1: Interrupt Control Register 1 (Continued)76Register 7-4: INTCON2: Interrupt Control Register 278Register 7-5: IFS0: Interrupt Flag Status Register 0 (Continued)79Register 7-6: IFS1: Interrupt Flag Status Register 181Register 7-7: IFS3: Interrupt Flag Status Register 382Register 7-8: IFS4: Interrupt Flag Status Register 483Register 7-9: IEC0: Interrupt Enable Control Register 0 (Continued)84Register 7-10: IEC1: Interrupt Enable Control Register 186Register 7-11: IEC3: Interrupt Enable Control Register 387Register 7-12: IEC4: Interrupt Enable Control Register 488Register 7-13: IPC0: Interrupt Priority Control Register 089Register 7-14: IPC1: Interrupt Priority Control Register 190Register 7-15: IPC2: Interrupt Priority Control Register 291Register 7-16: IPC3: Interrupt Priority Control Register 392Register 7-17: IPC4: Interrupt Priority Control Register 493Register 7-18: IPC5: Interrupt Priority Control Register 594Register 7-19: IPC7: Interrupt Priority Control Register 795Register 7-20: IPC14: Interrupt Priority Control Register 1496Register 7-21: IPC15: Interrupt Priority Control Register 1597Register 7-22: IPC16: Interrupt Priority Control Register 1697Register 7-23: IPC18: Interrupt Priority Control Register 1898Register 7-24: INTTREG: Interrupt Control and Status Register997.5 Interrupt Setup Procedures1008.0 Oscillator Configuration101FIGURE 8-1: dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 Oscillator System Diagram1018.1 CPU Clocking System102EQUATION 8-1: Device Operating Frequency102EQUATION 8-2: Fosc Calculation103EQUATION 8-3: XT with PLL Mode Example103FIGURE 8-2: dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 PLL Block Diagram103TABLE 8-1: Configuration Bit Values for Clock Selection1038.2 Oscillator Resources1048.3 Oscillator Control Registers105Register 8-1: OSCCON: Oscillator Control Register(1,3) (Continued)105Register 8-2: CLKDIV: Clock Divisor Register(2)107Register 8-3: PLLFBD: PLL Feedback Divisor Register(1)108Register 8-4: OSCTUN: FRC Oscillator Tuning Register(2)1098.4 Clock Switching Operation1108.5 Fail-Safe Clock Monitor (FSCM)1109.0 Power-Saving Features1119.1 Clock Frequency and Clock Switching1119.2 Instruction-Based Power-Saving Modes111EXAMPLE 9-1: PWRSAV Instruction Syntax1119.3 Doze Mode1129.4 Peripheral Module Disable1129.5 Power-Saving Resources1139.6 Power-Saving Control Registers114Register 9-1: PMD1: Peripheral Module Disable Control Register 1114Register 9-2: PMD2: Peripheral Module Disable Control Register 2115Register 9-3: PMD3: Peripheral Module Disable Control Register 311610.0 I/O Ports11710.1 Parallel I/O (PIO) Ports117FIGURE 10-1: Block Diagram of a Typical Shared Port Structure11710.2 Open-Drain Configuration11810.3 Configuring Analog Port Pins11810.4 I/O Port Write/Read Timing11810.5 Input Change Notification118EXAMPLE 10-1: Port Write/Read Example118EXAMPLE 10-2: PORT Bit Operations11810.6 Peripheral Pin Select119FIGURE 10-2: remappable MUX input for u1rx119TABLE 10-1: Selectable INPUT SOURCES (MAPS Input TO FUNCTION)(1)120FIGURE 10-3: multiplexing of remappable output for rpn121TABLE 10-2: OUTPUT selection for remappable pin (RPn)12110.7 I/O Helpful Tips12310.8 I/O Resources12310.9 Peripheral Pin Select Registers124Register 10-1: RPINR0: Peripheral Pin Select Input Register 0124Register 10-2: RPINR1: Peripheral Pin Select Input Register 1125Register 10-3: RPINR3: Peripheral Pin Select Input Register 3126Register 10-4: RPINR7: Peripheral Pin Select Input Register 7127Register 10-5: RPINR10: Peripheral Pin Select INPUT Register 10128Register 10-6: RPINR11: Peripheral Pin Select Input Register 11129Register 10-7: RPINR12: Peripheral Pin Select Input Register 12129Register 10-8: RPINR13: Peripheral Pin Select Input Register 13130Register 10-9: RPINR14: Peripheral Pin Select Output Register 14131Register 10-10: RPINR15: Peripheral Pin Select Input Register 15132Register 10-11: RPINR18: Peripheral Pin Select Input Register 18133Register 10-12: RPINR20: Peripheral Pin Select Input Register 20134Register 10-13: RPINR21: Peripheral Pin Select Input Register 21135Register 10-14: RPOR0: Peripheral Pin Select Output Register 0136Register 10-15: RPOR1: Peripheral Pin Select Output Register 1136Register 10-16: RPOR2: Peripheral Pin Select Output Register 2137Register 10-17: RPOR3: Peripheral Pin Select Output Register 3137Register 10-18: RPOR4: Peripheral Pin Select Output Register 4138Register 10-19: RPOR5: Peripheral Pin Select Output Register 5138Register 10-20: RPOR6: Peripheral Pin Select Output Register 6139Register 10-21: RPOR7: Peripheral Pin Select Output Register 7139Register 10-22: RPOR8: Peripheral Pin Select Output Register 8140Register 10-23: RPOR9: Peripheral Pin Select Output Register 9140Register 10-24: RPOR10: Peripheral Pin Select Output Register 10141Register 10-25: RPOR11: Peripheral Pin Select Output Register 11141Register 10-26: RPOR12: Peripheral Pin Select Output Register 1214211.0 Timer1143FIGURE 11-1: 16-bit Timer1 Module Block Diagram14311.1 Timer Resources14411.2 Timer1 Control Register145Register 11-1: T1CON: Timer1 Control Register14512.0 Timer2/3 feature14712.1 32-bit Operation14712.2 16-bit Operation147FIGURE 12-1: Timer2/3 (32-bit) Block Diagram(1)148FIGURE 12-2: Timer2 (16-bit) Block Diagram14812.3 Timer2/3 Control Registers149Register 12-1: T2CON Control Register149Register 12-2: T3CON Control Register15013.0 Input Capture151FIGURE 13-1: Input Capture Block Diagram15113.1 Input Capture Resources15213.2 Input Capture Registers153Register 13-1: ICxCON: Input Capture x Control Register15314.0 Output Compare155FIGURE 14-1: Output Compare Module Block Diagram15514.1 Output Compare Modes156TABLE 14-1: Output Compare Modes156FIGURE 14-2: Output Compare Operation15614.2 Output Compare Resources15714.3 Output Compare Control Register158Register 14-1: OCxCON: Output Compare x Control Register15815.0 Motor Control PWM Module15915.1 PWM1: 6-Channel PWM Module15915.2 PWM2: 2-Channel PWM Module159FIGURE 15-1: 6-Channel PWM Module Block Diagram (PWM1)160FIGURE 15-2: 2-Channel PWM Module Block Diagram (PWM2)16115.3 Motor Control Resources16215.4 PWM Control Registers163Register 15-1: PxTCON: PWM Time Base Control Register163Register 15-2: PxTMR: PWM Timer Count Value Register164Register 15-3: PxTPER: PWM Time Base Period Register164Register 15-4: PxSECMP: Special Event Compare Register165Register 15-5: PWMXCON1: PWM Control Register 1(2)166Register 15-6: PWMxCON2: PWM Control Register 2167Register 15-7: PxDTCON1: Dead-Time Control Register 1168Register 15-8: PxDTCON2: Dead-Time Control Register 2(1)169Register 15-9: PxFLTACON: Fault A Control Register(1)170Register 15-10: PxOVDCON: Override Control Register(1)171Register 15-11: PxDC1: PWM Duty Cycle Register 1172Register 15-12: P1DC2: PWM Duty Cycle Register 2172Register 15-13: P1DC3: PWM Duty Cycle Register 317216.0 Quadrature Encoder Interface (QEI) Module173FIGURE 16-1: Quadrature Encoder Interface Block Diagram17316.1 Ouadrature Encoder Interface Resources17416.2 Control and Status Registers174Register 16-1: QEIxCON: QEI Control Register (Continued)175Register 16-2: DFLTxCON: Digital Filter Control Register17717.0 Serial Peripheral Interface (SPI)179FIGURE 17-1: SPI Module Block Diagram17917.1 SPI Helpful Tips18017.2 SPI Resources18017.3 SPI Control Registers181Register 17-1: SPIxSTAT: SPIx Status and Control Register181Register 17-2: SPIxCON1: SPIx Control Register 1 (Continued)182Register 17-3: SPIxCON2: SPIx Control Register 218418.0 Inter-Integrated Circuit™ (I2C™)18518.1 Operating Modes185FIGURE 18-1: I2C™ Block Diagram (x = 1)18618.2 I2C Resources18718.3 I2C Registers18718.4 I2C Control Registers188Register 18-1: I2CxCON: I2Cx Control Register (Continued)188Register 18-2: I2CxSTAT: I2Cx Status Register (Continued)190Register 18-3: I2CxMSK: I2Cx Slave Mode Address Mask Register19219.0 Universal Asynchronous Receiver Transmitter (UART)193FIGURE 19-1: UART Simplified Block Diagram19319.1 UART Helpful Tips19419.2 UART Resources19419.3 UART Control Registers195Register 19-1: UxMODE: UARTx Mode Register (Continued)195Register 19-2: UxSTA: UARTx Status and Control Register (Continued)19720.0 10-bit/12-bit Analog-to-Digital Converter (ADC)19920.1 Key Features19920.2 ADC Initialization199FIGURE 20-1: ADC1 Module Block Diagram for dsPIC33FJ16MC304 and dsPIC33FJ32MC204 Devices200FIGURE 20-2: ADC1 Module Block Diagram FOR dsPIC33FJ32MC202 Device201FIGURE 20-3: ADC Conversion Clock Period Block Diagram20220.3 ADC Helpful Tips20220.4 ADC Resources20220.5 ADC Control Registers203Register 20-1: AD1CON1: ADC1 control register 1 (Continued)203Register 20-2: AD1CON2: ADC1 control register 2205Register 20-3: AD1CON3: ADC1 Control Register 3206Register 20-4: AD1CHS123: ADC1 INPUT Channel 1, 2, 3 select Register (Continued)207Register 20-5: AD1CHS0: ADC1 INPUT Channel 0 select Register209Register 20-6: AD1CSSL: ADC1 INPUT SCAN SELECT register Low(1,2)210Register 20-7: AD1PCFGL: ADC1 Port configuration register Low(1,2,3)21021.0 Special Features21121.1 Configuration Bits211TABLE 21-1: Device Configuration Register Map211TABLE 21-2: Configuration Bits Description (Continued)21221.2 On-Chip Voltage Regulator215FIGURE 21-1: Connections for the On-Chip Voltage Regulator(1,2,3)21521.3 BOR: Brown-out Reset (BOR)21521.4 Watchdog Timer (WDT)216FIGURE 21-2: WDT Block diagram21621.5 JTAG Interface21721.6 In-Circuit Serial Programming21721.7 In-Circuit Debugger21721.8 Code Protection and CodeGuard™ Security218TABLE 21-3: CODE FLASH SECURITY Segment SIZES FOR 32 KByte Devices218TABLE 21-4: CODE FLASH SECURITY Segment SIZES FOR 16 KByte Devices21822.0 Instruction Set Summary219TABLE 22-1: Symbols used in Opcode Descriptions (Continued)220TABLE 22-2: Instruction Set OVERVIEW (Continued)22223.0 Development Support22723.1 MPLAB Integrated Development Environment Software22723.2 MPLAB C Compilers for Various Device Families22823.3 HI-TECH C for Various Device Families22823.4 MPASM Assembler22823.5 MPLINK Object Linker/ MPLIB Object Librarian22823.6 MPLAB Assembler, Linker and Librarian for Various Device Families22823.7 MPLAB SIM Software Simulator22923.8 MPLAB REAL ICE In-Circuit Emulator System22923.9 MPLAB ICD 3 In-Circuit Debugger System22923.10 PICkit 3 In-Circuit Debugger/ Programmer and PICkit 3 Debug Express22923.11 PICkit 2 Development Programmer/Debugger and PICkit 2 Debug Express23023.12 MPLAB PM3 Device Programmer23023.13 Demonstration/Development Boards, Evaluation Kits, and Starter Kits23024.0 Electrical Characteristics23124.1 DC Characteristics232TABLE 24-1: Operating MIPS vs. Voltage232TABLE 24-2: Thermal Operating Conditions232TABLE 24-3: Thermal Packaging Characteristics232TABLE 24-4: DC Temperature and Voltage specifications233TABLE 24-5: DC Characteristics: Operating Current (Idd)234TABLE 24-6: DC Characteristics: Idle Current (iidle)235TABLE 24-7: DC Characteristics: Power-Down Current (Ipd)236TABLE 24-8: DC Characteristics: doze Current (Idoze)237TABLE 24-9: DC Characteristics: I/O Pin Input Specifications (Continued)238TABLE 24-10: DC Characteristics: I/O Pin Output Specifications241TABLE 24-11: Electrical Characteristics: BOR242TABLE 24-12: DC Characteristics: Program Memory242TABLE 24-13: Internal Voltage Regulator Specifications24324.2 AC Characteristics and Timing Parameters244TABLE 24-14: Temperature and Voltage Specifications – AC244FIGURE 24-1: Load Conditions for Device Timing Specifications244TABLE 24-15: cAPAcITIVE lOADING rEQUIREMENTS ON oUTPUT pINS244FIGURE 24-2: External Clock Timing245TABLE 24-16: External Clock Timing Requirements245TABLE 24-17: PLL Clock Timing Specifications (Vdd = 3.0V to 3.6V)246TABLE 24-18: AC Characteristics: Internal RC Accuracy246TABLE 24-19: Internal RC accuracy246FIGURE 24-3: I/O Timing Characteristics247TABLE 24-20: I/O Timing Requirements247FIGURE 24-4: Reset, Watchdog Timer, Oscillator Start-up Timer and Power-up Timer Timing Characteristics248TABLE 24-21: Reset, Watchdog Timer, Oscillator Start-up Timer, Power-up Timer Timing Requirements249FIGURE 24-5: Timer1, 2 and 3 External Clock Timing Characteristics250TABLE 24-22: Timer1 External Clock Timing Requirements(1)250TABLE 24-23: Timer2 External Clock Timing Requirements251TABLE 24-24: Timer3 External Clock Timing Requirements251FIGURE 24-6: TimerQ (QEI Module) External Clock Timing Characteristics252TABLE 24-25: QEI module External Clock Timing Requirements252FIGURE 24-7: INPUT CAPTURE (CAPx) TIMING Characteristics253TABLE 24-26: Input Capture timing requirements253FIGURE 24-8: Output Compare Module (OCx) Timing Characteristics253TABLE 24-27: Output Compare Module timing requirements253FIGURE 24-9: OC/PWM Module Timing Characteristics254TABLE 24-28: Simple OC/PWM MODE Timing Requirements254FIGURE 24-10: Motor Control PWM Module fault Timing Characteristics255FIGURE 24-11: Motor Control PWM Module Timing Characteristics255TABLE 24-29: Motor Control PWM Module Timing Requirements255FIGURE 24-12: QEA/QEB Input Characteristics256TABLE 24-30: Quadrature Decoder Timing Requirements256FIGURE 24-13: QEI Module Index Pulse Timing Characteristics257TABLE 24-31: QEI INDEX PULSE Timing Requirements257TABLE 24-32: SPIx Maximum Data/CLock Rate Summary258FIGURE 24-14: SPIx MASTER MODE (Half-Duplex, Transmit Only CKE = 0) TIMING CHARACTERISTICS258FIGURE 24-15: SPIx MASTER MODE (Half-Duplex, Transmit Only CKE = 1) TIMING CHARACTERISTICS259TABLE 24-33: SPIx Master Mode (Half-Duplex, Transmit Only) Timing Requirements259FIGURE 24-16: SPIx MASTER MODE (Full-Duplex, CKE = 1, CKP = X, SMP = 1) TIMING CHARACTERISTICS260TABLE 24-34: SPIx Master Mode (Full-Duplex, CKE = 1, CKP = x, SMP = 1) Timing Requirements260FIGURE 24-17: SPIx MASTER MODE (Full-Duplex, CKE = 0, CKP = X, SMP = 1) TIMING CHARACTERISTICS261TABLE 24-35: SPIx Master Mode (Full-Duplex, CKE = 0, CKP = x, SMP = 1) Timing Requirements261FIGURE 24-18: SPIx SLAVE MODE (Full-Duplex, CKE = 1, CKP = 0, SMP = 0) TIMING CHARACTERISTICS262TABLE 24-36: SPIx Slave Mode (Full-Duplex, CKE = 1, CKP = 0, SMP = 0) Timing Requirements263FIGURE 24-19: SPIx SLAVE MODE (Full-Duplex, CKE = 1, CKP = 1, SMP = 0) TIMING CHARACTERISTICS264TABLE 24-37: SPIx Slave Mode (Full-Duplex, CKE = 1, CKP = 1, SMP = 0) Timing Requirements265FIGURE 24-20: SPIx SLAVE MODE (Full-Duplex CKE = 0, CKP = 1, SMP = 0) TIMING CHARACTERISTICS266TABLE 24-38: SPIx Slave Mode (Full-Duplex, CKE = 0, CKP = 1, SMP = 0) Timing Requirements267FIGURE 24-21: SPIx SLAVE MODE (Full-Duplex, CKE = 0, CKP = 0, SMP = 0) TIMING CHARACTERISTICS268TABLE 24-39: SPIx Slave Mode (Full-Duplex, CKE = 0, CKP = 0, SMP = 0) Timing Requirements269FIGURE 24-22: I2Cx Bus Start/Stop Bits Timing Characteristics (Master Mode)270FIGURE 24-23: I2Cx Bus Data Timing Characteristics (Master mode)270TABLE 24-40: I2Cx Bus Data Timing Requirements (Master Mode)271FIGURE 24-24: I2Cx Bus Start/Stop Bits Timing Characteristics (slave mode)272FIGURE 24-25: I2Cx Bus Data Timing Characteristics (slave mode)272TABLE 24-41: I2Cx Bus Data Timing Requirements (Slave Mode)273TABLE 24-42: ADC Module Specifications274TABLE 24-43: ADC Module Specifications (12-bit Mode)275TABLE 24-44: ADC Module Specifications (10-bit Mode)276FIGURE 24-26: ADC Conversion (12-bit mode) Timing Characteristics (asam = 0, ssrc<2:0> = 000)277TABLE 24-45: ADC Conversion (12-bit Mode) TiminG rEQUIREMENTS277FIGURE 24-27: ADC Conversion (10-bit mode) Timing Characteristics (chps<1:0> = 01, SIMSAM = 0, asam = 0, ssrc<2:0> = 000)278FIGURE 24-28: ADC Conversion (10-bit mode) Timing cHARACTERISTICS (chps<1:0> = 01, SIMSAM = 0, asam = 1, ssrc<2:0> = 111, SAMC<4:0> = 00001)278TABLE 24-46: ADC CONVERSION (10-bit mode) TIMING rEQUIREMENTS27925.0 High Temperature Electrical Characteristics28125.1 High Temperature DC Characteristics282TABLE 25-1: Operating MIPS vs. Voltage282TABLE 25-2: Thermal Operating Conditions282TABLE 25-3: DC Temperature and Voltage Specifications282TABLE 25-4: DC Characteristics: Power-down Current (Ipd)283TABLE 25-5: DC Characteristics: Operating Current (Idd)283TABLE 25-6: DC Characteristics: Doze Current (Idoze)283TABLE 25-7: DC Characteristics: I/O Pin Output Specifications28425.2 AC Characteristics and Timing Parameters285TABLE 25-8: Temperature and Voltage Specifications – AC285FIGURE 25-1: Load Conditions for Device Timing Specifications285TABLE 25-9: PLL Clock Timing Specifications285TABLE 25-10: SPIx Master Mode (cke = 0) Timing Requirements286TABLE 25-11: SPIx Module Master Mode (cke = 1) Timing Requirements286TABLE 25-12: SPIx Module Slave Mode (cke = 0) Timing Requirements287TABLE 25-13: SPIx Module Slave Mode (cke = 1) Timing Requirements287TABLE 25-14: Internal RC accuracy287TABLE 25-15: ADC Module Specifications288TABLE 25-16: ADC Module Specifications (12-bit Mode)(3)288TABLE 25-17: ADC Module Specifications (10-bit Mode)(3)289TABLE 25-18: ADC Conversion (12-bit Mode) Timing Requirements290TABLE 25-19: ADC Conversion (10-bit mode) Timing Requirements29026.0 DC and AC Device Characteristics Graphs291FIGURE 26-1: Voh – 2x Driver Pins291FIGURE 26-2: Voh – 4x Driver Pins291FIGURE 26-3: Voh – 8x Driver Pins291FIGURE 26-4: Voh – 16x Driver Pins291FIGURE 26-5: Vol – 2x Driver Pins292FIGURE 26-6: Vol – 4x Driver Pins292FIGURE 26-7: Vol – 8x Driver Pins292FIGURE 26-8: Vol – 16x Driver Pins292FIGURE 26-9: Typical Ipd Current @ Vdd = 3.3V, +85ºC293FIGURE 26-10: Typical Idd Current @ Vdd = 3.3V, +85ºC293FIGURE 26-11: Typical Idoze Current @ Vdd = 3.3V, +85ºC293FIGURE 26-12: Typical Iidle Current @ Vdd = 3.3V, +85ºC293FIGURE 26-13: Typical FRC Frequency @ Vdd = 3.3V294FIGURE 26-14: Typical LPRC Frequency @ Vdd = 3.3V29427.0 Packaging Information29527.1 Package Marking Information29527.1 Package Marking Information (Continued)29627.2 Package Details297Appendix A: Revision History309TABLE A-1: Major Section Updates (Continued)310TABLE A-2: Major Section Updates314TABLE A-3: Major Section Updates315TABLE A-4: Major Section Updates316TABLE A-5: Major Section Updates316TABLE A-6: Major Section Updates (Continued)317TABLE A-7: Major Section Updates319TABLE A-8: Major Section Updates319INDEX321Dimensioni: 4,8 MBPagine: 330Language: EnglishApri il manuale