Microchip Technology DM330023-2 マニュアル

目次

• 1.0 Device Overview

  9
  • FIGURE 1-1: dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 Block Diagram

    10
  • TABLE 1-1: Pinout I/O Descriptions (Continued)

    11
• 2.0 Guidelines for Getting Started with 16-bit Digital Signal Controllers

  13
  • 2.1 Basic Connection Requirements

    13
  • 2.2 Decoupling Capacitors

    13
    • FIGURE 2-1: Recommended Minimum connection

      14
  • 2.3 CPU Logic Filter Capacitor Connection (Vcap)

    14
  • 2.4 Master Clear (MCLR) Pin

    14
    • FIGURE 2-2: Example of MCLR Pin Connections

      14
  • 2.5 ICSP Pins

    15
  • 2.6 External Oscillator Pins

    15
    • FIGURE 2-3: Suggested Placement of the Oscillator Circuit

      15
  • 2.7 Oscillator Value Conditions on Device Start-up

    16
  • 2.8 Configuration of Analog and Digital Pins During ICSP Operations

    16
  • 2.9 Unused I/Os

    16
• 3.0 CPU

  17
  • 3.1 Data Addressing Overview

    17
  • 3.2 DSP Engine Overview

    17
  • 3.3 Special MCU Features

    18
    • FIGURE 3-1: dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 CPU Core Block Diagram

      18
    • FIGURE 3-2: dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 Programmer’s Model

      19
  • 3.4 CPU Resources

    20
  • 3.5 CPU Control Registers

    21
    • Register 3-1: SR: CPU STATUS Register (Continued)

      21
    • Register 3-2: CORCON: CORE Control Register

      23
  • 3.6 Arithmetic Logic Unit (ALU)

    24
  • 3.7 DSP Engine

    24
    • TABLE 3-1: DSP Instructions Summary

      24
    • FIGURE 3-3: DSP Engine Block Diagram

      25
• 4.0 Memory Organization

  29
  • 4.1 Program Address Space

    29
    • FIGURE 4-1: Program Memory Maps for dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 Devices

      29
    • FIGURE 4-2: Program Memory Organization

      30
  • 4.2 Data Address Space

    31
    • FIGURE 4-3: Data Memory Map for dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 Devices with 2 Kb RAM

      32
  • 4.3 Program Memory Resources

    33
  • 4.4 Special Function Register Maps

    34
    • TABLE 4-1: CPU Core Registers Map (Continued)

      34
    • TABLE 4-2: Change Notification Register Map for dsPIC33FJ32MC202

      35
    • TABLE 4-3: Change Notification Register Map for dsPIC33FJ32MC204 and dsPIC33FJ16MC304

      35
    • TABLE 4-4: Interrupt Controller Register Map

      36
    • TABLE 4-5: Timer Register Map

      37
    • TABLE 4-6: Input Capture Register Map

      37
    • TABLE 4-7: Output Compare Register Map

      37
    • TABLE 4-8: 6-Output PWM1 Register Map

      38
    • TABLE 4-9: 2-Output PWM2 Register Map

      38
    • TABLE 4-10: QEI1 Register Map

      39
    • TABLE 4-11: I2C1 Register Map

      39
    • TABLE 4-12: UART1 Register Map

      39
    • TABLE 4-13: SPI1 Register Map

      39
    • TABLE 4-14: ADC1 Register Map for dsPIC33FJ32MC202

      40
    • TABLE 4-15: ADC1 Register Map for dsPIC33FJ32MC204 and dsPIC33FJ16MC304

      41
    • TABLE 4-16: PERIPHERAL pin select INPUT Register Map

      42
    • TABLE 4-17: PERIPHERAL pin select outPUT Register Map for dsPIC33FJ32MC202

      42
    • TABLE 4-18: pERIPHERAL pin select outPUT Register Map for dsPIC33FJ32MC204 AND dsPIC33FJ16MC304

      43
    • TABLE 4-19: PORTA Register Map FOR dsPIC33FJ32MC202

      43
    • TABLE 4-20: PORTA Register Map for dsPIC33FJ32MC204 AND dsPIC33FJ16MC304

      43
    • TABLE 4-21: PORTB Register Map

      44
    • TABLE 4-22: PORTC Register Map for dsPIC33FJ32MC204 AND dsPIC33FJ16MC304

      44
    • TABLE 4-23: System Control Register Map

      44
    • TABLE 4-24: NVM Register Map

      45
    • TABLE 4-25: PMD Register Map

      45
    • FIGURE 4-4: CALL Stack Frame

      46
  • 4.5 Instruction Addressing Modes

    46
    • TABLE 4-26: Fundamental Addressing Modes Supported

      47
  • 4.6 Modulo Addressing

    48
    • FIGURE 4-5: Modulo Addressing Operation Example

      48
  • 4.7 Bit-Reversed Addressing

    49
    • FIGURE 4-6: Bit-Reversed Address Example

      50
    • TABLE 4-27: Bit-Reversed Address Sequence (16-Entry)

      50
  • 4.8 Interfacing Program and Data Memory Spaces

    51
    • TABLE 4-28: Program Space Address Construction

      51
    • FIGURE 4-7: Data Access from Program Space Address Generation

      52
    • FIGURE 4-8: Accessing Program Memory with Table Instructions

      53
    • FIGURE 4-9: Program Space Visibility Operation

      54
• 5.0 Flash Program Memory

  55
  • 5.1 Table Instructions and Flash Programming

    55
    • FIGURE 5-1: Addressing for Table Registers

      55
  • 5.2 RTSP Operation

    56
  • 5.3 Programming Operations

    56
    • EQUATION 5-1: programming time

      56
    • EQUATION 5-2: Minimum Row Write Time

      56
    • EQUATION 5-3: Maximum Row Write Time

      56
  • 5.4 Flash Memory Resources

    56
  • 5.5 Control Registers

    56
    • Register 5-1: NVMCON: Flash Memory Control Register

      57
    • Register 5-2: NVMKEY: NonVolatile Memory Key RegisteR

      58
    • EXAMPLE 5-1: Erasing a Program Memory Page

      59
    • EXAMPLE 5-2: Loading the Write Buffers

      60
    • EXAMPLE 5-3: Initiating a Programming Sequence

      60
• 6.0 Resets

  61
  • FIGURE 6-1: Reset System Block Diagram

    61
  • 6.1 Resets Resources

    62
  • 6.2 Reset Control Registers

    63
    • Register 6-1: RCON: Reset Control Register(1) (Continued)

      63
  • 6.3 System Reset

    65
    • TABLE 6-1: Oscillator Parameters

      65
    • FIGURE 6-2: System Reset Timing

      66
    • TABLE 6-2: Oscillator Delay

      67
  • 6.4 Power-on Reset (POR)

    67
  • 6.4.1 Brown-out Reset (BOR) and Power-up timer (PWRT)

    67
    • FIGURE 6-3: Brown-out Situations

      68
  • 6.5 External Reset (EXTR)

    68
  • 6.6 Software RESET Instruction (SWR)

    68
  • 6.7 Watchdog Time-out Reset (WDTO)

    68
  • 6.8 Trap Conflict Reset

    68
  • 6.9 Configuration Mismatch Reset

    69
  • 6.10 Illegal Condition Device Reset

    69
  • 6.11 Using the RCON Status Bits

    69
    • TABLE 6-3: Reset Flag Bit Operation

      69
• 7.0 Interrupt Controller

  71
  • 7.1 Interrupt Vector Table

    71
  • 7.2 Reset Sequence

    71
    • FIGURE 7-1: dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 Interrupt Vector Table

      72
    • TABLE 7-1: Interrupt Vectors

      73
    • TABLE 7-2: Trap Vectors

      73
  • 7.3 Interrupt Resources

    74
  • 7.4 Interrupt Control and Status Registers

    74
    • Register 7-1: SR: CPU STATUS Register(1)

      75
    • Register 7-2: CORCON: CORE Control Register(1)

      75
    • Register 7-3: INTCON1: Interrupt Control Register 1 (Continued)

      76
    • Register 7-4: INTCON2: Interrupt Control Register 2

      78
    • Register 7-5: IFS0: Interrupt Flag Status Register 0 (Continued)

      79
    • Register 7-6: IFS1: Interrupt Flag Status Register 1

      81
    • Register 7-7: IFS3: Interrupt Flag Status Register 3

      82
    • Register 7-8: IFS4: Interrupt Flag Status Register 4

      83
    • Register 7-9: IEC0: Interrupt Enable Control Register 0 (Continued)

      84
    • Register 7-10: IEC1: Interrupt Enable Control Register 1

      86
    • Register 7-11: IEC3: Interrupt Enable Control Register 3

      87
    • Register 7-12: IEC4: Interrupt Enable Control Register 4

      88
    • Register 7-13: IPC0: Interrupt Priority Control Register 0

      89
    • Register 7-14: IPC1: Interrupt Priority Control Register 1

      90
    • Register 7-15: IPC2: Interrupt Priority Control Register 2

      91
    • Register 7-16: IPC3: Interrupt Priority Control Register 3

      92
    • Register 7-17: IPC4: Interrupt Priority Control Register 4

      93
    • Register 7-18: IPC5: Interrupt Priority Control Register 5

      94
    • Register 7-19: IPC7: Interrupt Priority Control Register 7

      95
    • Register 7-20: IPC14: Interrupt Priority Control Register 14

      96
    • Register 7-21: IPC15: Interrupt Priority Control Register 15

      97
    • Register 7-22: IPC16: Interrupt Priority Control Register 16

      97
    • Register 7-23: IPC18: Interrupt Priority Control Register 18

      98
    • Register 7-24: INTTREG: Interrupt Control and Status Register

      99
  • 7.5 Interrupt Setup Procedures

    100
• 8.0 Oscillator Configuration

  101
  • FIGURE 8-1: dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 Oscillator System Diagram

    101
  • 8.1 CPU Clocking System

    102
    • EQUATION 8-1: Device Operating Frequency

      102
    • EQUATION 8-2: Fosc Calculation

      103
    • EQUATION 8-3: XT with PLL Mode Example

      103
    • FIGURE 8-2: dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 PLL Block Diagram

      103
    • TABLE 8-1: Configuration Bit Values for Clock Selection

      103
  • 8.2 Oscillator Resources

    104
  • 8.3 Oscillator Control Registers

    105
    • Register 8-1: OSCCON: Oscillator Control Register(1,3) (Continued)

      105
    • Register 8-2: CLKDIV: Clock Divisor Register(2)

      107
    • Register 8-3: PLLFBD: PLL Feedback Divisor Register(1)

      108
    • Register 8-4: OSCTUN: FRC Oscillator Tuning Register(2)

      109
  • 8.4 Clock Switching Operation

    110
  • 8.5 Fail-Safe Clock Monitor (FSCM)

    110
• 9.0 Power-Saving Features

  111
  • 9.1 Clock Frequency and Clock Switching

    111
  • 9.2 Instruction-Based Power-Saving Modes

    111
    • EXAMPLE 9-1: PWRSAV Instruction Syntax

      111
  • 9.3 Doze Mode

    112
  • 9.4 Peripheral Module Disable

    112
  • 9.5 Power-Saving Resources

    113
  • 9.6 Power-Saving Control Registers

    114
    • Register 9-1: PMD1: Peripheral Module Disable Control Register 1

      114
    • Register 9-2: PMD2: Peripheral Module Disable Control Register 2

      115
    • Register 9-3: PMD3: Peripheral Module Disable Control Register 3

      116
• 10.0 I/O Ports

  117
  • 10.1 Parallel I/O (PIO) Ports

    117
    • FIGURE 10-1: Block Diagram of a Typical Shared Port Structure

      117
  • 10.2 Open-Drain Configuration

    118
  • 10.3 Configuring Analog Port Pins

    118
  • 10.4 I/O Port Write/Read Timing

    118
  • 10.5 Input Change Notification

    118
    • EXAMPLE 10-1: Port Write/Read Example

      118
    • EXAMPLE 10-2: PORT Bit Operations

      118
  • 10.6 Peripheral Pin Select

    119
    • FIGURE 10-2: remappable MUX input for u1rx

      119
    • TABLE 10-1: Selectable INPUT SOURCES (MAPS Input TO FUNCTION)(1)

      120
    • FIGURE 10-3: multiplexing of remappable output for rpn

      121
    • TABLE 10-2: OUTPUT selection for remappable pin (RPn)

      121
  • 10.7 I/O Helpful Tips

    123
  • 10.8 I/O Resources

    123
  • 10.9 Peripheral Pin Select Registers

    124
    • Register 10-1: RPINR0: Peripheral Pin Select Input Register 0

      124
    • Register 10-2: RPINR1: Peripheral Pin Select Input Register 1

      125
    • Register 10-3: RPINR3: Peripheral Pin Select Input Register 3

      126
    • Register 10-4: RPINR7: Peripheral Pin Select Input Register 7

      127
    • Register 10-5: RPINR10: Peripheral Pin Select INPUT Register 10

      128
    • Register 10-6: RPINR11: Peripheral Pin Select Input Register 11

      129
    • Register 10-7: RPINR12: Peripheral Pin Select Input Register 12

      129
    • Register 10-8: RPINR13: Peripheral Pin Select Input Register 13

      130
    • Register 10-9: RPINR14: Peripheral Pin Select Output Register 14

      131
    • Register 10-10: RPINR15: Peripheral Pin Select Input Register 15

      132
    • Register 10-11: RPINR18: Peripheral Pin Select Input Register 18

      133
    • Register 10-12: RPINR20: Peripheral Pin Select Input Register 20

      134
    • Register 10-13: RPINR21: Peripheral Pin Select Input Register 21

      135
    • Register 10-14: RPOR0: Peripheral Pin Select Output Register 0

      136
    • Register 10-15: RPOR1: Peripheral Pin Select Output Register 1

      136
    • Register 10-16: RPOR2: Peripheral Pin Select Output Register 2

      137
    • Register 10-17: RPOR3: Peripheral Pin Select Output Register 3

      137
    • Register 10-18: RPOR4: Peripheral Pin Select Output Register 4

      138
    • Register 10-19: RPOR5: Peripheral Pin Select Output Register 5

      138
    • Register 10-20: RPOR6: Peripheral Pin Select Output Register 6

      139
    • Register 10-21: RPOR7: Peripheral Pin Select Output Register 7

      139
    • Register 10-22: RPOR8: Peripheral Pin Select Output Register 8

      140
    • Register 10-23: RPOR9: Peripheral Pin Select Output Register 9

      140
    • Register 10-24: RPOR10: Peripheral Pin Select Output Register 10

      141
    • Register 10-25: RPOR11: Peripheral Pin Select Output Register 11

      141
    • Register 10-26: RPOR12: Peripheral Pin Select Output Register 12

      142
• 11.0 Timer1

  143
  • FIGURE 11-1: 16-bit Timer1 Module Block Diagram

    143
  • 11.1 Timer Resources

    144
  • 11.2 Timer1 Control Register

    145
    • Register 11-1: T1CON: Timer1 Control Register

      145
• 12.0 Timer2/3 feature

  147
  • 12.1 32-bit Operation

    147
  • 12.2 16-bit Operation

    147
    • FIGURE 12-1: Timer2/3 (32-bit) Block Diagram(1)

      148
    • FIGURE 12-2: Timer2 (16-bit) Block Diagram

      148
  • 12.3 Timer2/3 Control Registers

    149
    • Register 12-1: T2CON Control Register

      149
    • Register 12-2: T3CON Control Register

      150
• 13.0 Input Capture

  151
  • FIGURE 13-1: Input Capture Block Diagram

    151
  • 13.1 Input Capture Resources

    152
  • 13.2 Input Capture Registers

    153
    • Register 13-1: ICxCON: Input Capture x Control Register

      153
• 14.0 Output Compare

  155
  • FIGURE 14-1: Output Compare Module Block Diagram

    155
  • 14.1 Output Compare Modes

    156
    • TABLE 14-1: Output Compare Modes

      156
    • FIGURE 14-2: Output Compare Operation

      156
  • 14.2 Output Compare Resources

    157
  • 14.3 Output Compare Control Register

    158
    • Register 14-1: OCxCON: Output Compare x Control Register

      158
• 15.0 Motor Control PWM Module

  159
  • 15.1 PWM1: 6-Channel PWM Module

    159
  • 15.2 PWM2: 2-Channel PWM Module

    159
    • FIGURE 15-1: 6-Channel PWM Module Block Diagram (PWM1)

      160
    • FIGURE 15-2: 2-Channel PWM Module Block Diagram (PWM2)

      161
  • 15.3 Motor Control Resources

    162
  • 15.4 PWM Control Registers

    163
    • Register 15-1: PxTCON: PWM Time Base Control Register

      163
    • Register 15-2: PxTMR: PWM Timer Count Value Register

      164
    • Register 15-3: PxTPER: PWM Time Base Period Register

      164
    • Register 15-4: PxSECMP: Special Event Compare Register

      165
    • Register 15-5: PWMXCON1: PWM Control Register 1(2)

      166
    • Register 15-6: PWMxCON2: PWM Control Register 2

      167
    • Register 15-7: PxDTCON1: Dead-Time Control Register 1

      168
    • Register 15-8: PxDTCON2: Dead-Time Control Register 2(1)

      169
    • Register 15-9: PxFLTACON: Fault A Control Register(1)

      170
    • Register 15-10: PxOVDCON: Override Control Register(1)

      171
    • Register 15-11: PxDC1: PWM Duty Cycle Register 1

      172
    • Register 15-12: P1DC2: PWM Duty Cycle Register 2

      172
    • Register 15-13: P1DC3: PWM Duty Cycle Register 3

      172
• 16.0 Quadrature Encoder Interface (QEI) Module

  173
  • FIGURE 16-1: Quadrature Encoder Interface Block Diagram

    173
  • 16.1 Ouadrature Encoder Interface Resources

    174
  • 16.2 Control and Status Registers

    174
    • Register 16-1: QEIxCON: QEI Control Register (Continued)

      175
    • Register 16-2: DFLTxCON: Digital Filter Control Register

      177
• 17.0 Serial Peripheral Interface (SPI)

  179
  • FIGURE 17-1: SPI Module Block Diagram

    179
  • 17.1 SPI Helpful Tips

    180
  • 17.2 SPI Resources

    180
  • 17.3 SPI Control Registers

    181
    • Register 17-1: SPIxSTAT: SPIx Status and Control Register

      181
    • Register 17-2: SPIxCON1: SPIx Control Register 1 (Continued)

      182
    • Register 17-3: SPIxCON2: SPIx Control Register 2

      184
• 18.0 Inter-Integrated Circuit™ (I2C™)

  185
  • 18.1 Operating Modes

    185
    • FIGURE 18-1: I2C™ Block Diagram (x = 1)

      186
  • 18.2 I2C Resources

    187
  • 18.3 I2C Registers

    187
  • 18.4 I2C Control Registers

    188
    • Register 18-1: I2CxCON: I2Cx Control Register (Continued)

      188
    • Register 18-2: I2CxSTAT: I2Cx Status Register (Continued)

      190
    • Register 18-3: I2CxMSK: I2Cx Slave Mode Address Mask Register

      192
• 19.0 Universal Asynchronous Receiver Transmitter (UART)

  193
  • FIGURE 19-1: UART Simplified Block Diagram

    193
  • 19.1 UART Helpful Tips

    194
  • 19.2 UART Resources

    194
  • 19.3 UART Control Registers

    195
    • Register 19-1: UxMODE: UARTx Mode Register (Continued)

      195
    • Register 19-2: UxSTA: UARTx Status and Control Register (Continued)

      197
• 20.0 10-bit/12-bit Analog-to-Digital Converter (ADC)

  199
  • 20.1 Key Features

    199
  • 20.2 ADC Initialization

    199
    • FIGURE 20-1: ADC1 Module Block Diagram for dsPIC33FJ16MC304 and dsPIC33FJ32MC204 Devices

      200
    • FIGURE 20-2: ADC1 Module Block Diagram FOR dsPIC33FJ32MC202 Device

      201
    • FIGURE 20-3: ADC Conversion Clock Period Block Diagram

      202
  • 20.3 ADC Helpful Tips

    202
  • 20.4 ADC Resources

    202
  • 20.5 ADC Control Registers

    203
    • Register 20-1: AD1CON1: ADC1 control register 1 (Continued)

      203
    • Register 20-2: AD1CON2: ADC1 control register 2

      205
    • Register 20-3: AD1CON3: ADC1 Control Register 3

      206
    • Register 20-4: AD1CHS123: ADC1 INPUT Channel 1, 2, 3 select Register (Continued)

      207
    • Register 20-5: AD1CHS0: ADC1 INPUT Channel 0 select Register

      209
    • Register 20-6: AD1CSSL: ADC1 INPUT SCAN SELECT register Low(1,2)

      210
    • Register 20-7: AD1PCFGL: ADC1 Port configuration register Low(1,2,3)

      210
• 21.0 Special Features

  211
  • 21.1 Configuration Bits

    211
    • TABLE 21-1: Device Configuration Register Map

      211
    • TABLE 21-2: Configuration Bits Description (Continued)

      212
  • 21.2 On-Chip Voltage Regulator

    215
    • FIGURE 21-1: Connections for the On-Chip Voltage Regulator(1,2,3)

      215
  • 21.3 BOR: Brown-out Reset (BOR)

    215
  • 21.4 Watchdog Timer (WDT)

    216
    • FIGURE 21-2: WDT Block diagram

      216
  • 21.5 JTAG Interface

    217
  • 21.6 In-Circuit Serial Programming

    217
  • 21.7 In-Circuit Debugger

    217
  • 21.8 Code Protection and CodeGuard™ Security

    218
    • TABLE 21-3: CODE FLASH SECURITY Segment SIZES FOR 32 KByte Devices

      218
    • TABLE 21-4: CODE FLASH SECURITY Segment SIZES FOR 16 KByte Devices

      218
• 22.0 Instruction Set Summary

  219
  • TABLE 22-1: Symbols used in Opcode Descriptions (Continued)

    220
  • TABLE 22-2: Instruction Set OVERVIEW (Continued)

    222
• 23.0 Development Support

  227
  • 23.1 MPLAB Integrated Development Environment Software

    227
  • 23.2 MPLAB C Compilers for Various Device Families

    228
  • 23.3 HI-TECH C for Various Device Families

    228
  • 23.4 MPASM Assembler

    228
  • 23.5 MPLINK Object Linker/ MPLIB Object Librarian

    228
  • 23.6 MPLAB Assembler, Linker and Librarian for Various Device Families

    228
  • 23.7 MPLAB SIM Software Simulator

    229
  • 23.8 MPLAB REAL ICE In-Circuit Emulator System

    229
  • 23.9 MPLAB ICD 3 In-Circuit Debugger System

    229
  • 23.10 PICkit 3 In-Circuit Debugger/ Programmer and PICkit 3 Debug Express

    229
  • 23.11 PICkit 2 Development Programmer/Debugger and PICkit 2 Debug Express

    230
  • 23.12 MPLAB PM3 Device Programmer

    230
  • 23.13 Demonstration/Development Boards, Evaluation Kits, and Starter Kits

    230
• 24.0 Electrical Characteristics

  231
  • 24.1 DC Characteristics

    232
    • TABLE 24-1: Operating MIPS vs. Voltage

      232
    • TABLE 24-2: Thermal Operating Conditions

      232
    • TABLE 24-3: Thermal Packaging Characteristics

      232
    • TABLE 24-4: DC Temperature and Voltage specifications

      233
    • TABLE 24-5: DC Characteristics: Operating Current (Idd)

      234
    • TABLE 24-6: DC Characteristics: Idle Current (iidle)

      235
    • TABLE 24-7: DC Characteristics: Power-Down Current (Ipd)

      236
    • TABLE 24-8: DC Characteristics: doze Current (Idoze)

      237
    • TABLE 24-9: DC Characteristics: I/O Pin Input Specifications (Continued)

      238
    • TABLE 24-10: DC Characteristics: I/O Pin Output Specifications

      241
    • TABLE 24-11: Electrical Characteristics: BOR

      242
    • TABLE 24-12: DC Characteristics: Program Memory

      242
    • TABLE 24-13: Internal Voltage Regulator Specifications

      243
  • 24.2 AC Characteristics and Timing Parameters

    244
    • TABLE 24-14: Temperature and Voltage Specifications – AC

      244
    • FIGURE 24-1: Load Conditions for Device Timing Specifications

      244
    • TABLE 24-15: cAPAcITIVE lOADING rEQUIREMENTS ON oUTPUT pINS

      244
    • FIGURE 24-2: External Clock Timing

      245
    • TABLE 24-16: External Clock Timing Requirements

      245
    • TABLE 24-17: PLL Clock Timing Specifications (Vdd = 3.0V to 3.6V)

      246
    • TABLE 24-18: AC Characteristics: Internal RC Accuracy

      246
    • TABLE 24-19: Internal RC accuracy

      246
    • FIGURE 24-3: I/O Timing Characteristics

      247
    • TABLE 24-20: I/O Timing Requirements

      247
    • FIGURE 24-4: Reset, Watchdog Timer, Oscillator Start-up Timer and Power-up Timer Timing Characteristics

      248
    • TABLE 24-21: Reset, Watchdog Timer, Oscillator Start-up Timer, Power-up Timer Timing Requirements

      249
    • FIGURE 24-5: Timer1, 2 and 3 External Clock Timing Characteristics

      250
    • TABLE 24-22: Timer1 External Clock Timing Requirements(1)

      250
    • TABLE 24-23: Timer2 External Clock Timing Requirements

      251
    • TABLE 24-24: Timer3 External Clock Timing Requirements

      251
    • FIGURE 24-6: TimerQ (QEI Module) External Clock Timing Characteristics

      252
    • TABLE 24-25: QEI module External Clock Timing Requirements

      252
    • FIGURE 24-7: INPUT CAPTURE (CAPx) TIMING Characteristics

      253
    • TABLE 24-26: Input Capture timing requirements

      253
    • FIGURE 24-8: Output Compare Module (OCx) Timing Characteristics

      253
    • TABLE 24-27: Output Compare Module timing requirements

      253
    • FIGURE 24-9: OC/PWM Module Timing Characteristics

      254
    • TABLE 24-28: Simple OC/PWM MODE Timing Requirements

      254
    • FIGURE 24-10: Motor Control PWM Module fault Timing Characteristics

      255
    • FIGURE 24-11: Motor Control PWM Module Timing Characteristics

      255
    • TABLE 24-29: Motor Control PWM Module Timing Requirements

      255
    • FIGURE 24-12: QEA/QEB Input Characteristics

      256
    • TABLE 24-30: Quadrature Decoder Timing Requirements

      256
    • FIGURE 24-13: QEI Module Index Pulse Timing Characteristics

      257
    • TABLE 24-31: QEI INDEX PULSE Timing Requirements

      257
    • TABLE 24-32: SPIx Maximum Data/CLock Rate Summary

      258
    • FIGURE 24-14: SPIx MASTER MODE (Half-Duplex, Transmit Only CKE = 0) TIMING CHARACTERISTICS

      258
    • FIGURE 24-15: SPIx MASTER MODE (Half-Duplex, Transmit Only CKE = 1) TIMING CHARACTERISTICS

      259
    • TABLE 24-33: SPIx Master Mode (Half-Duplex, Transmit Only) Timing Requirements

      259
    • FIGURE 24-16: SPIx MASTER MODE (Full-Duplex, CKE = 1, CKP = X, SMP = 1) TIMING CHARACTERISTICS

      260
    • TABLE 24-34: SPIx Master Mode (Full-Duplex, CKE = 1, CKP = x, SMP = 1) Timing Requirements

      260
    • FIGURE 24-17: SPIx MASTER MODE (Full-Duplex, CKE = 0, CKP = X, SMP = 1) TIMING CHARACTERISTICS

      261
    • TABLE 24-35: SPIx Master Mode (Full-Duplex, CKE = 0, CKP = x, SMP = 1) Timing Requirements

      261
    • FIGURE 24-18: SPIx SLAVE MODE (Full-Duplex, CKE = 1, CKP = 0, SMP = 0) TIMING CHARACTERISTICS

      262
    • TABLE 24-36: SPIx Slave Mode (Full-Duplex, CKE = 1, CKP = 0, SMP = 0) Timing Requirements

      263
    • FIGURE 24-19: SPIx SLAVE MODE (Full-Duplex, CKE = 1, CKP = 1, SMP = 0) TIMING CHARACTERISTICS

      264
    • TABLE 24-37: SPIx Slave Mode (Full-Duplex, CKE = 1, CKP = 1, SMP = 0) Timing Requirements

      265
    • FIGURE 24-20: SPIx SLAVE MODE (Full-Duplex CKE = 0, CKP = 1, SMP = 0) TIMING CHARACTERISTICS

      266
    • TABLE 24-38: SPIx Slave Mode (Full-Duplex, CKE = 0, CKP = 1, SMP = 0) Timing Requirements

      267
    • FIGURE 24-21: SPIx SLAVE MODE (Full-Duplex, CKE = 0, CKP = 0, SMP = 0) TIMING CHARACTERISTICS

      268
    • TABLE 24-39: SPIx Slave Mode (Full-Duplex, CKE = 0, CKP = 0, SMP = 0) Timing Requirements

      269
    • FIGURE 24-22: I2Cx Bus Start/Stop Bits Timing Characteristics (Master Mode)

      270
    • FIGURE 24-23: I2Cx Bus Data Timing Characteristics (Master mode)

      270
    • TABLE 24-40: I2Cx Bus Data Timing Requirements (Master Mode)

      271
    • FIGURE 24-24: I2Cx Bus Start/Stop Bits Timing Characteristics (slave mode)

      272
    • FIGURE 24-25: I2Cx Bus Data Timing Characteristics (slave mode)

      272
    • TABLE 24-41: I2Cx Bus Data Timing Requirements (Slave Mode)

      273
    • TABLE 24-42: ADC Module Specifications

      274
    • TABLE 24-43: ADC Module Specifications (12-bit Mode)

      275
    • TABLE 24-44: ADC Module Specifications (10-bit Mode)

      276
    • FIGURE 24-26: ADC Conversion (12-bit mode) Timing Characteristics (asam = 0, ssrc<2:0> = 000)

      277
    • TABLE 24-45: ADC Conversion (12-bit Mode) TiminG rEQUIREMENTS

      277
    • FIGURE 24-27: ADC Conversion (10-bit mode) Timing Characteristics (chps<1:0> = 01, SIMSAM = 0, asam = 0, ssrc<2:0> = 000)

      278
    • FIGURE 24-28: ADC Conversion (10-bit mode) Timing cHARACTERISTICS (chps<1:0> = 01, SIMSAM = 0, asam = 1, ssrc<2:0> = 111, SAMC<4:0> = 00001)

      278
    • TABLE 24-46: ADC CONVERSION (10-bit mode) TIMING rEQUIREMENTS

      279
• 25.0 High Temperature Electrical Characteristics

  281
  • 25.1 High Temperature DC Characteristics

    282
    • TABLE 25-1: Operating MIPS vs. Voltage

      282
    • TABLE 25-2: Thermal Operating Conditions

      282
    • TABLE 25-3: DC Temperature and Voltage Specifications

      282
    • TABLE 25-4: DC Characteristics: Power-down Current (Ipd)

      283
    • TABLE 25-5: DC Characteristics: Operating Current (Idd)

      283
    • TABLE 25-6: DC Characteristics: Doze Current (Idoze)

      283
    • TABLE 25-7: DC Characteristics: I/O Pin Output Specifications

      284
  • 25.2 AC Characteristics and Timing Parameters

    285
    • TABLE 25-8: Temperature and Voltage Specifications – AC

      285
    • FIGURE 25-1: Load Conditions for Device Timing Specifications

      285
    • TABLE 25-9: PLL Clock Timing Specifications

      285
    • TABLE 25-10: SPIx Master Mode (cke = 0) Timing Requirements

      286
    • TABLE 25-11: SPIx Module Master Mode (cke = 1) Timing Requirements

      286
    • TABLE 25-12: SPIx Module Slave Mode (cke = 0) Timing Requirements

      287
    • TABLE 25-13: SPIx Module Slave Mode (cke = 1) Timing Requirements

      287
    • TABLE 25-14: Internal RC accuracy

      287
    • TABLE 25-15: ADC Module Specifications

      288
    • TABLE 25-16: ADC Module Specifications (12-bit Mode)(3)

      288
    • TABLE 25-17: ADC Module Specifications (10-bit Mode)(3)

      289
    • TABLE 25-18: ADC Conversion (12-bit Mode) Timing Requirements

      290
    • TABLE 25-19: ADC Conversion (10-bit mode) Timing Requirements

      290
• 26.0 DC and AC Device Characteristics Graphs

  291
  • FIGURE 26-1: Voh – 2x Driver Pins

    291
  • FIGURE 26-2: Voh – 4x Driver Pins

    291
  • FIGURE 26-3: Voh – 8x Driver Pins

    291
  • FIGURE 26-4: Voh – 16x Driver Pins

    291
  • FIGURE 26-5: Vol – 2x Driver Pins

    292
  • FIGURE 26-6: Vol – 4x Driver Pins

    292
  • FIGURE 26-7: Vol – 8x Driver Pins

    292
  • FIGURE 26-8: Vol – 16x Driver Pins

    292
  • FIGURE 26-9: Typical Ipd Current @ Vdd = 3.3V, +85ºC

    293
  • FIGURE 26-10: Typical Idd Current @ Vdd = 3.3V, +85ºC

    293
  • FIGURE 26-11: Typical Idoze Current @ Vdd = 3.3V, +85ºC

    293
  • FIGURE 26-12: Typical Iidle Current @ Vdd = 3.3V, +85ºC

    293
  • FIGURE 26-13: Typical FRC Frequency @ Vdd = 3.3V

    294
  • FIGURE 26-14: Typical LPRC Frequency @ Vdd = 3.3V

    294
• 27.0 Packaging Information

  295
  • 27.1 Package Marking Information

    295
  • 27.1 Package Marking Information (Continued)

    296
  • 27.2 Package Details

    297
• Appendix A: Revision History

  309
  • TABLE A-1: Major Section Updates (Continued)

    310
  • TABLE A-2: Major Section Updates

    314
  • TABLE A-3: Major Section Updates

    315
  • TABLE A-4: Major Section Updates

    316
  • TABLE A-5: Major Section Updates

    316
  • TABLE A-6: Major Section Updates (Continued)

    317
  • TABLE A-7: Major Section Updates

    319
  • TABLE A-8: Major Section Updates

    319
• INDEX

  321