Scheda Tecnica (TMDXRM46CNCD)Sommario1 RM46Lx50 16- and 32-Bit RISC Flash Microcontroller11.1 Features11.2 Applications21.3 Description31.4 Functional Block Diagram5Table of Contents7Revision History82 Device Package and Terminal Functions92.1 PGE QFP Package Pinout (144-Pin)92.2 ZWT BGA Package Ball-Map (337 Ball Grid Array)102.3 Terminal Functions112.3.1 PGE Package112.3.1.1 Multi-Buffered Analog-to-Digital Converters (MibADC)112.3.1.2 Enhanced High-End Timer Modules (N2HET)132.3.1.3 Enhanced Capture Modules (eCAP)142.3.1.4 Enhanced Quadrature Encoder Pulse Modules (eQEP)152.3.1.5 Enhanced Pulse-Width Modulator Modules (ePWM)162.3.1.6 General-Purpose Input / Output (GPIO)172.3.1.7 Controller Area Network Controllers (DCAN)172.3.1.8 Local Interconnect Network Interface Module (LIN)172.3.1.9 Standard Serial Communication Interface (SCI)182.3.1.10 Inter-Integrated Circuit Interface Module (I2C)182.3.1.11 Standard Serial Peripheral Interface (SPI)182.3.1.12 Multi-Buffered Serial Peripheral Interface Modules (MibSPI)192.3.1.13 Ethernet Controller202.3.1.14 USB Host Port Controller Interface212.3.1.15 System Module Interface222.3.1.16 Clock Inputs and Outputs232.3.1.17 Test and Debug Modules Interface232.3.1.18 Flash Supply and Test Pads232.3.1.19 Supply for Core Logic: 1.2V nominal242.3.1.20 Supply for I/O Cells: 3.3V nominal242.3.1.21 Ground Reference for All Supplies Except VCCAD252.3.2 ZWT Package262.3.2.1 Multi-Buffered Analog-to-Digital Converters (MibADC)262.3.2.2 Enhanced High-End Timer Modules (N2HET)272.3.2.3 Enhanced Capture Modules (eCAP)282.3.2.4 Enhanced Quadrature Encoder Pulse Modules (eQEP)292.3.2.5 Enhanced Pulse-Width Modulator Modules (ePWM)302.3.2.6 General-Purpose Input / Output (GPIO)312.3.2.7 Controller Area Network Controllers (DCAN)322.3.2.8 Local Interconnect Network Interface Module (LIN)322.3.2.9 Standard Serial Communication Interface (SCI)322.3.2.10 Inter-Integrated Circuit Interface Module (I2C)332.3.2.11 Standard Serial Peripheral Interface (SPI)332.3.2.12 Multi-Buffered Serial Peripheral Interface Modules (MibSPI)342.3.2.13 Ethernet Controller362.3.2.14 USB Host Port Controller Interface382.3.2.15 External Memory Interface (EMIF)402.3.2.16 System Module Interface422.3.2.17 Clock Inputs and Outputs422.3.2.18 Test and Debug Modules Interface432.3.2.19 Flash Supply and Test Pads432.3.2.20 No Connects432.3.2.21 Supply for Core Logic: 1.2V nominal462.3.2.22 Supply for I/O Cells: 3.3V nominal472.3.2.23 Ground Reference for All Supplies Except VCCAD483 Device Operating Conditions493.1 Absolute Maximum Ratings Over Operating Free-Air Temperature Range,493.2 Device Recommended Operating Conditions493.3 Switching Characteristics over Recommended Operating Conditions for Clock Domains503.4 Wait States Required503.5 Power Consumption Over Recommended Operating Conditions513.6 Input/Output Electrical Characteristics Over Recommended Operating Conditions523.7 Output Buffer Drive Strengths533.8 Input Timings543.9 Output Timings543.10 Low-EMI Output Buffers564 System Information and Electrical Specifications574.1 Device Power Domains574.2 Voltage Monitor Characteristics574.2.1 Important Considerations574.2.2 Voltage Monitor Operation574.2.3 Supply Filtering584.3 Power Sequencing and Power On Reset594.3.1 Power-Up Sequence594.3.2 Power-Down Sequence594.3.3 Power-On Reset: nPORRST594.3.3.1 nPORRST Electrical and Timing Requirements594.4 Warm Reset (nRST)614.4.1 Causes of Warm Reset614.4.2 nRST Timing Requirements614.5 ARM© Cortex-R4F™ CPU Information624.5.1 Summary of ARM Cortex-R4F™ CPU Features624.5.2 ARM Cortex-R4F™ CPU Features Enabled by Software624.5.3 Dual Core Implementation624.5.4 Duplicate clock tree after GCLK634.5.5 ARM Cortex-R4F™ CPU Compare Module (CCM-R4) for Safety634.5.6 CPU Self-Test634.5.6.1 Application Sequence for CPU Self-Test644.5.6.2 CPU Self-Test Clock Configuration644.5.6.3 CPU Self-Test Coverage644.6 Clocks654.6.1 Clock Sources654.6.1.1 Main Oscillator654.6.1.2 Low Power Oscillator674.6.1.3 Phase Locked Loop (PLL) Clock Modules684.6.1.4 External Clock Inputs694.6.2 Clock Domains694.6.2.1 Clock Domain Descriptions694.6.2.2 Mapping of Clock Domains to Device Modules714.6.2.3 Special Clock Source Selection Scheme for VCLKA4_DIVR_EMAC724.6.3 Clock Test Mode734.7 Clock Monitoring744.7.1 Clock Monitor Timings744.7.2 External Clock (ECLK) Output Functionality744.7.3 Dual Clock Comparators744.7.3.1 Features744.7.3.2 Mapping of DCC Clock Source Inputs754.8 Glitch Filters764.9 Device Memory Map774.9.1 Memory Map Diagram774.9.2 Memory Map Table784.9.3 Special Consideration for CPU Access Errors Resulting in Imprecise Aborts824.9.4 Master/Slave Access Privileges824.9.5 Special Notes on Accesses to Certain Slaves824.9.6 Parameter Overlay Module (POM) Considerations824.10 Flash Memory844.10.1 Flash Memory Configuration844.10.2 Main Features of Flash Module844.10.3 ECC Protection for Flash Accesses854.10.4 Flash Access Speeds854.10.5 Program Flash864.10.6 Data Flash864.11 Tightly-Coupled RAM Interface Module874.11.1 Features874.11.2 TCRAMW ECC Support874.12 Parity Protection for Accesses to peripheral RAMs874.13 On-Chip SRAM Initialization and Testing894.13.1 On-Chip SRAM Self-Test Using PBIST894.13.1.1 Features894.13.1.2 PBIST RAM Groups894.13.2 On-Chip SRAM Auto Initialization904.14 External Memory Interface (EMIF)914.14.1 Features914.14.2 Electrical and Timing Specifications914.14.2.1 Asynchronous RAM914.14.2.2 Synchronous Timing964.15 Vectored Interrupt Manager994.15.1 VIM Features994.15.2 Interrupt Request Assignments994.16 DMA Controller1034.16.1 DMA Features1034.16.2 Default DMA Request Map1044.17 Real Time Interrupt Module1064.17.1 Features1064.17.2 Block Diagrams1064.17.3 Clock Source Options1074.17.4 Network Time Synchronization Inputs1074.18 Error Signaling Module1084.18.1 Features1084.18.2 ESM Channel Assignments1084.19 Reset / Abort / Error Sources1124.20 Digital Windowed Watchdog1154.21 Debug Subsystem1164.21.1 Block Diagram1164.21.2 Debug Components Memory Map1164.21.3 JTAG Identification Code1164.21.4 Debug ROM1164.21.5 JTAG Scan Interface Timings1184.21.6 Advanced JTAG Security Module1194.21.7 Boundary Scan Chain1205 Peripheral Information and Electrical Specifications1215.1 Enhanced Translator PWM Modules (ePWM)1215.1.1 ePWM Clocking and Reset1225.1.2 Synchronization of ePWMx Time Base Counters1225.1.3 Synchronizing all ePWM Modules to the N2HET1 Module Time Base1225.1.4 Phase-Locking the Time-Base Clocks of Multiple ePWM Modules1235.1.5 ePWM Synchronization with External Devices1235.1.6 ePWM Trip Zones1235.1.6.1 Trip Zones TZ1n, TZ2n, TZ3n1235.1.6.2 Trip Zone TZ4n1235.1.6.3 Trip Zone TZ5n1245.1.6.4 Trip Zone TZ6n1245.1.7 Triggering of ADC Start of Conversion Using ePWMx SOCA and SOCB Outputs1245.1.8 Enhanced Translator-Pulse Width Modulator (ePWMx) Timings1245.2 Enhanced Capture Modules (eCAP)1265.2.1 Clock Enable Control for eCAPx Modules1265.2.2 PWM Output Capability of eCAPx1275.2.3 Input Connection to eCAPx Modules1275.2.4 Enhanced Capture Module (eCAP) Timings1275.3 Enhanced Quadrature Encoder (eQEP)1285.3.1 Clock Enable Control for eQEPx Modules1285.3.2 Using eQEPx Phase Error to Trip ePWMx Outputs1285.3.3 Input Connections to eQEPx Modules1285.3.4 Enhanced Quadrature Encoder Pulse (eQEPx) Timing1295.4 Multi-Buffered 12bit Analog-to-Digital Converter1305.4.1 Features1305.4.2 Event Trigger Options1305.4.2.1 MIBADC1 Event Trigger Hookup1305.4.2.2 MIBADC2 Event Trigger Hookup1315.4.2.3 Controlling ADC1 and ADC2 Event Trigger Options Using SOC Output from ePWM Modules1325.4.3 ADC Electrical and Timing Specifications1355.4.4 Performance (Accuracy) Specifications1385.4.4.1 MibADC Nonlinearity Errors1385.4.4.2 MibADC Total Error1405.5 General-Purpose Input/Output1415.5.1 Features1415.6 Enhanced High-End Timer (N2HET)1425.6.1 Features1425.6.2 N2HET RAM Organization1425.6.3 Input Timing Specifications1425.6.4 N2HET1-N2HET2 Synchronization1435.6.5 N2HET Checking1435.6.5.1 Internal Monitoring1435.6.5.2 Output Monitoring using Dual Clock Comparator (DCC)1435.6.6 Disabling N2HET Outputs1445.6.7 High-End Timer Transfer Unit (HTU)1455.6.7.1 Features1455.6.7.2 Trigger Connections1455.7 Controller Area Network (DCAN)1465.7.1 Features1465.7.2 Electrical and Timing Specifications1465.8 Local Interconnect Network Interface (LIN)1475.8.1 LIN Features1475.9 Serial Communication Interface (SCI)1485.9.1 Features1485.10 Inter-Integrated Circuit (I2C)1495.10.1 Features1495.10.2 I2C I/O Timing Specifications1505.11 Multi-Buffered / Standard Serial Peripheral Interface1525.11.1 Features1525.11.2 MibSPI Transmit and Receive RAM Organization1525.11.3 MibSPI Transmit Trigger Events1525.11.3.1 MIBSPI1 Event Trigger Hookup1535.11.3.2 MIBSPI3 Event Trigger Hookup1535.11.3.3 MIBSPI5 Event Trigger Hookup1545.11.4 MibSPI/SPI Master Mode I/O Timing Specifications1565.11.5 SPI Slave Mode I/O Timings1605.12 Ethernet Media Access Controller1645.12.1 Ethernet MII Electrical and Timing Specifications1645.12.2 Ethernet RMII Timing1665.12.3 Management Data Input/Output (MDIO)1675.13 Universal Serial Bus Controller1685.13.1 Features1685.13.2 Electrical and Timing Specifications1686 Device and Documentation Support1706.1 Device and Development-Support Tool Nomenclature1706.2 Community Resources1706.3 Device Identification1716.3.1 Device Identification Code Register1716.3.2 Die Identification Registers1726.4 Module Certifications1736.4.1 DCAN Certification1746.4.2 LIN Certification1756.4.2.1 LIN Master Mode1756.4.2.2 LIN Slave Mode - Fixed Baud Rate1766.4.2.3 LIN Slave Mode - Adaptive Baud Rate1777 Mechanical Data1787.1 Thermal Data1787.2 Packaging Information178Dimensioni: 8,71 MBPagine: 183Language: EnglishApri il manuale