Manuali utente per Texas Instruments SPRU938B

Sommario

• Table of Contents

  3
• Preface

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• 1 Introduction

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  • 1.1 Purpose of the Peripheral

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  • 1.2 Features

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  • 1.3 Functional Block Diagram

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  • 1.4 Industry Standard(s) Compliance Statement

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• 2 Peripheral Architecture

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  • 2.1 Clock Control

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  • 2.2 Signal Descriptions

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  • 2.3 Pin Multiplexing

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  • 2.4 Protocol Description

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  • 2.5 VLYNQ Functional Description

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    • 2.5.1 Write Operations

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    • 2.5.2 Read Operations

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  • 2.6 Initialization

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  • 2.7 Auto-Negotiation

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  • 2.8 Address Translation

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  • 2.9 Flow Control

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  • 2.10 Reset Considerations

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    • 2.10.1 Software Reset Considerations

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    • 2.10.2 Hardware Reset Considerations

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  • 2.11 Interrupt Support

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    • 2.11.1 Interrupt Events and Requests

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    • 2.11.2 Writes to Interrupt Pending/Set Register

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    • 2.11.3 Remote Interrupts

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    • 2.11.4 Serial Bus Error Interrupts

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  • 2.12 EDMA Event Support

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  • 2.13 Power Management

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  • 2.14 Endianness Considerations

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  • 2.15 Emulation Considerations

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• 3 VLYNQ Port Registers

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  • 3.1 Revision Register (REVID)

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  • 3.2 Control Register (CTRL)

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  • 3.3 Status Register (STAT)

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  • 3.4 Interrupt Priority Vector Status/Clear Register (INTPRI)

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  • 3.5 Interrupt Status/Clear Register (INTSTATCLR)

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  • 3.6 Interrupt Pending/Set Register (INTPENDSET)

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  • 3.7 Interrupt Pointer Register (INTPTR)

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  • 3.8 Transmit Address Map Register (XAM)

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  • 3.9 Receive Address Map Size 1 Register (RAMS1)

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  • 3.10 Receive Address Map Offset 1 Register (RAMO1)

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  • 3.11 Receive Address Map Size 2 Register (RAMS2)

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  • 3.12 Receive Address Map Offset 2 Register (RAMO2)

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  • 3.13 Receive Address Map Size 3 Register (RAMS3)

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  • 3.14 Receive Address Map Offset 3 Register (RAMO3)

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  • 3.15 Receive Address Map Size 4 Register (RAMS4)

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  • 3.16 Receive Address Map Offset 4 Register (RAMO4)

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  • 3.17 Chip Version Register (CHIPVER)

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  • 3.18 Auto Negotiation Register (AUTNGO)

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• 4 Remote Configuration Registers

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• Appendix A VLYNQ Protocol Specifications

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  • A.1 Introduction

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  • A.2 Special 8b/10b Code Groups

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  • A.3 Supported Ordered Sets

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    • A.3.1 Idle (/I/)

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    • A.3.2 End of Packet (/T/)

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    • A.3.3 Byte Disable (/M/)

      40
    • A.3.4 Flow Control Enable (/P/)

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    • A.3.5 Flow Control Disable (/C/)

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    • A.3.6 Error Indication (/E/)

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    • A.3.7 Init0 (/0/)

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    • A.3.8 Init1 (/1/)

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    • A.3.9 Link (/L/)

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  • A.4 VLYNQ 2.0 Packet Format

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  • A.5 VLYNQ 2.X Packets

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• Appendix B Write/Read Performance

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  • B.1 Introduction

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  • B.2 Write Performance

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  • B.3 Read Performance

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• Appendix C Revision History

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