用户手册 — Texas Instruments SPRU938B

目录

• Table of Contents

  3
• Preface

  7
• 1 Introduction

  8
  • 1.1 Purpose of the Peripheral

    8
  • 1.2 Features

    8
  • 1.3 Functional Block Diagram

    9
  • 1.4 Industry Standard(s) Compliance Statement

    9
• 2 Peripheral Architecture

  10
  • 2.1 Clock Control

    10
  • 2.2 Signal Descriptions

    11
  • 2.3 Pin Multiplexing

    11
  • 2.4 Protocol Description

    11
  • 2.5 VLYNQ Functional Description

    12
    • 2.5.1 Write Operations

      13
    • 2.5.2 Read Operations

      14
  • 2.6 Initialization

    15
  • 2.7 Auto-Negotiation

    15
  • 2.8 Address Translation

    16
  • 2.9 Flow Control

    19
  • 2.10 Reset Considerations

    20
    • 2.10.1 Software Reset Considerations

      20
    • 2.10.2 Hardware Reset Considerations

      20
  • 2.11 Interrupt Support

    20
    • 2.11.1 Interrupt Events and Requests

      20
    • 2.11.2 Writes to Interrupt Pending/Set Register

      21
    • 2.11.3 Remote Interrupts

      22
    • 2.11.4 Serial Bus Error Interrupts

      22
  • 2.12 EDMA Event Support

    22
  • 2.13 Power Management

    23
  • 2.14 Endianness Considerations

    23
  • 2.15 Emulation Considerations

    23
• 3 VLYNQ Port Registers

  24
  • 3.1 Revision Register (REVID)

    25
  • 3.2 Control Register (CTRL)

    26
  • 3.3 Status Register (STAT)

    28
  • 3.4 Interrupt Priority Vector Status/Clear Register (INTPRI)

    30
  • 3.5 Interrupt Status/Clear Register (INTSTATCLR)

    30
  • 3.6 Interrupt Pending/Set Register (INTPENDSET)

    31
  • 3.7 Interrupt Pointer Register (INTPTR)

    31
  • 3.8 Transmit Address Map Register (XAM)

    32
  • 3.9 Receive Address Map Size 1 Register (RAMS1)

    33
  • 3.10 Receive Address Map Offset 1 Register (RAMO1)

    33
  • 3.11 Receive Address Map Size 2 Register (RAMS2)

    34
  • 3.12 Receive Address Map Offset 2 Register (RAMO2)

    34
  • 3.13 Receive Address Map Size 3 Register (RAMS3)

    35
  • 3.14 Receive Address Map Offset 3 Register (RAMO3)

    35
  • 3.15 Receive Address Map Size 4 Register (RAMS4)

    36
  • 3.16 Receive Address Map Offset 4 Register (RAMO4)

    36
  • 3.17 Chip Version Register (CHIPVER)

    37
  • 3.18 Auto Negotiation Register (AUTNGO)

    37
• 4 Remote Configuration Registers

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• Appendix A VLYNQ Protocol Specifications

  39
  • A.1 Introduction

    39
  • A.2 Special 8b/10b Code Groups

    39
  • A.3 Supported Ordered Sets

    39
    • A.3.1 Idle (/I/)

      40
    • A.3.2 End of Packet (/T/)

      40
    • A.3.3 Byte Disable (/M/)

      40
    • A.3.4 Flow Control Enable (/P/)

      40
    • A.3.5 Flow Control Disable (/C/)

      40
    • A.3.6 Error Indication (/E/)

      40
    • A.3.7 Init0 (/0/)

      40
    • A.3.8 Init1 (/1/)

      40
    • A.3.9 Link (/L/)

      40
  • A.4 VLYNQ 2.0 Packet Format

    40
  • A.5 VLYNQ 2.X Packets

    42
• Appendix B Write/Read Performance

  44
  • B.1 Introduction

    44
  • B.2 Write Performance

    44
  • B.3 Read Performance

    46
• Appendix C Revision History

  47