Manuali utente per Texas Instruments TMS320C645x DSP

Sommario

• Table of Contents

  3
• Preface

  10
• 1 Introduction

  11
  • 1.1 Purpose of the Peripheral

    11
  • 1.2 Features

    11
  • 1.3 Functional Block Diagram

    12
  • 1.4 Industry Standard(s) Compliance Statement

    13
• 2 EMAC Functional Architecture

  14
  • 2.1 Clock Control

    14
    • 2.1.1 MII Clocking

      14
    • 2.1.2 RMII Clocking

      14
    • 2.1.3 GMII Clocking

      14
    • 2.1.4 RGMII Clocking

      15
  • 2.2 Memory Map

    15
  • 2.3 System Level Connections

    16
    • 2.3.1 Media Independent Interface (MII) Connections

      16
    • 2.3.2 Reduced Media Independent Interface (RMII) Connections

      18
    • 2.3.3 Gigabit Media Independent Interface (GMII) Connections

      20
    • 2.3.4 Reduced Gigabit Media Independent Interface (RGMII) Connections

      22
  • 2.4 Ethernet Protocol Overview

    24
    • 2.4.1 Ethernet Frame Format

      24
    • 2.4.2  Multiple Access Protocol

      25
  • 2.5 Programming Interface

    26
    • 2.5.1 Packet Buffer Descriptors

      26
    • 2.5.2 Transmit and Receive Descriptor Queues

      28
    • 2.5.3 Transmit and Receive EMAC Interrupts

      29
    • 2.5.4 Transmit Buffer Descriptor Format

      30
      • 2.5.4.1 Next Descriptor Pointer

        31
      • 2.5.4.2 Buffer Pointer

        31
      • 2.5.4.3 Buffer Offset

        31
      • 2.5.4.4 Buffer Length

        31
      • 2.5.4.5 Packet Length

        31
      • 2.5.4.6 Start of Packet (SOP) Flag

        31
      • 2.5.4.7 End of Packet (EOP) Flag

        32
      • 2.5.4.8 Ownership (OWNER) Flag

        32
      • 2.5.4.9 End of Queue (EOQ) Flag

        32
      • 2.5.4.10 Teardown Complete (TDOWNCMPLT) Flag

        32
      • 2.5.4.11 Pass CRC (PASSCRC) Flag

        32
    • 2.5.5 Receive Buffer Descriptor Format

      33
      • 2.5.5.1 Next Descriptor Pointer

        34
      • 2.5.5.2 Buffer Pointer

        34
      • 2.5.5.3 Buffer Offset

        34
      • 2.5.5.4 Buffer Length

        34
      • 2.5.5.5 Packet Length

        34
      • 2.5.5.6 Start of Packet (SOP) Flag

        35
      • 2.5.5.7 End of Packet (EOP) Flag

        35
      • 2.5.5.8 Ownership (OWNER) Flag

        35
      • 2.5.5.9 End of Queue (EOQ) Flag

        35
      • 2.5.5.10 Teardown Complete (TDOWNCMPLT) Flag

        35
      • 2.5.5.11 Pass CRC (PASSCRC) Flag

        35
      • 2.5.5.12 Jabber Flag

        35
      • 2.5.5.13 Oversize Flag

        35
      • 2.5.5.14 Fragment Flag

        36
      • 2.5.5.15 Undersized Flag

        36
      • 2.5.5.16 Control Flag

        36
      • 2.5.5.17 Overrun Flag

        36
      • 2.5.5.18 Code Error (CODEERROR) Flag

        36
      • 2.5.5.19 Alignment Error (ALIGNERROR) Flag

        36
      • 2.5.5.20 CRC Error (CRCERROR) Flag

        36
      • 2.5.5.21 No Match (NOMATCH) Flag

        36
  • 2.6 EMAC Control Module

    37
    • 2.6.1 Internal Memory

      37
    • 2.6.2 Bus Arbiter

      37
    • 2.6.3 Interrupt Control

      38
  • 2.7 Management Data Input/Output (MDIO) Module

    38
    • 2.7.1 MDIO Module Components

      38
      • 2.7.1.1 MDIO Clock Generator

        39
      • 2.7.1.2 Global PHY Detection and Link State Monitoring

        39
      • 2.7.1.3 Active PHY Monitoring

        39
      • 2.7.1.4 PHY Register User Access

        39
    • 2.7.2 MDIO Module Operational Overview

      40
      • 2.7.2.1 Initializing the MDIO Module

        40
      • 2.7.2.2 Writing Data to a PHY Register

        41
      • 2.7.2.3 Reading Data From a PHY Register

        41
      • 2.7.2.4 Example of MDIO Register Access Code

        41
  • 2.8 EMAC Module

    43
    • 2.8.1 EMAC Module Components

      43
      • 2.8.1.1 Receive DMA Engine

        43
      • 2.8.1.2 Receive FIFO

        43
      • 2.8.1.3 MAC Receiver

        44
      • 2.8.1.4 Receive Address

        44
      • 2.8.1.5 Transmit DMA Engine

        44
      • 2.8.1.6 Transmit FIFO

        44
      • 2.8.1.7 MAC Transmitter

        44
      • 2.8.1.8 Statistics Logic

        44
      • 2.8.1.9 State RAM

        44
      • 2.8.1.10 EMAC Interrupt Controller

        44
      • 2.8.1.11 Control Registers and Logic

        44
      • 2.8.1.12 Clock and Reset Logic

        45
    • 2.8.2 EMAC Module Operational Overview

      45
  • 2.9 Media Independent Interfaces

    46
    • 2.9.1 Data Reception

      46
      • 2.9.1.1 Receive Control

        46
      • 2.9.1.2 Receive Inter-Frame Interval

        46
      • 2.9.1.3 Receive Flow Control

        46
      • 2.9.1.4 Collision-Based Receive Buffer Flow Control

        47
      • 2.9.1.5 IEEE 802.3X Based Receive Buffer Flow Control

        47
    • 2.9.2 Data Transmission

      48
      • 2.9.2.1 Transmit Control

        48
      • 2.9.2.2 CRC Insertion

        48
      • 2.9.2.3 Adaptive Performance Optimization (APO)

        48
      • 2.9.2.4 Interpacket-Gap (IPG) Enforcement

        48
      • 2.9.2.5 Back Off

        48
      • 2.9.2.6 Transmit Flow Control

        49
      • 2.9.2.7 Speed, Duplex, and Pause Frame Support

        49
  • 2.10 Packet Receive Operation

    50
    • 2.10.1 Receive DMA Host Configuration

      50
    • 2.10.2 Receive Channel Enabling

      50
    • 2.10.3 Receive Channel Addressing

      51
    • 2.10.4 Hardware Receive QOS Support

      51
    • 2.10.5 Host Free Buffer Tracking

      52
    • 2.10.6 Receive Channel Teardown

      52
    • 2.10.7 Receive Frame Classification

      52
    • 2.10.8 Promiscuous Receive Mode

      53
    • 2.10.9 Receive Overrun

      54
  • 2.11 Packet Transmit Operation

    55
    • 2.11.1 Transmit DMA Host Configuration

      55
    • 2.11.2 Transmit Channel Teardown

      55
  • 2.12 Receive and Transmit Latency

    55
  • 2.13 Transfer Node Priority

    56
  • 2.14 Reset Considerations

    56
    • 2.14.1 Software Reset Considerations

      56
    • 2.14.2 Hardware Reset Considerations

      56
  • 2.15 Initialization

    57
    • 2.15.1 Enabling the EMAC/MDIO Peripheral

      57
    • 2.15.2 EMAC Control Module Initialization

      57
    • 2.15.3 MDIO Module Initialization

      58
    • 2.15.4 EMAC Module Initialization

      59
  • 2.16 Interrupt Support

    60
    • 2.16.1 EMAC Module Interrupt Events and Requests

      60
      • 2.16.1.1 Transmit Packet Completion Interrupts

        60
      • 2.16.1.2 Receive Packet Completion Interrupts

        61
      • 2.16.1.3 Statistics Interrupt

        61
      • 2.16.1.4 Host Error Interrupt

        62
    • 2.16.2 MDIO Module Interrupt Events and Requests

      62
      • 2.16.2.1 Link Change Interrupt

        62
      • 2.16.2.2 User Access Completion Interrupt

        62
    • 2.16.3 Proper Interrupt Processing

      63
    • 2.16.4 Interrupt Multiplexing

      63
  • 2.17 Power Management

    63
  • 2.18 Emulation Considerations

    63
• 3 EMAC Control Module Registers

  64
  • 3.1 Introduction

    64
  • 3.2 EMAC Control Module Interrupt Control Register (EWCTL)

    64
  • 3.3 EMAC Control Module Interrupt Timer Count Register (EWINTTCNT)

    65
• 4 MDIO Registers

  66
  • 4.1 Introduction

    66
  • 4.2 MDIO Version Register (VERSION)

    67
  • 4.3 MDIO Control Register (CONTROL)

    68
  • 4.4 PHY Acknowledge Status Register (ALIVE)

    69
  • 4.5 PHY Link Status Register (LINK)

    70
  • 4.6 MDIO Link Status Change Interrupt (Unmasked) Register (LINKINTRAW)

    71
  • 4.7 MDIO Link Status Change Interrupt (Masked) Register (LINKINTMASKED)

    72
  • 4.8 MDIO User Command Complete Interrupt (Unmasked) Register (USERINTRAW)

    73
  • 4.9 MDIO User Command Complete Interrupt (Masked) Register (USERINTMASKED)

    74
  • 4.10 MDIO User Command Complete Interrupt Mask Set Register (USERINTMASKSET)

    75
  • 4.11 MDIO User Command Complete Interrupt Mask Clear Register (USERINTMASKCLEAR)

    76
  • 4.12 MDIO User Access Register 0 (USERACCESS0)

    77
  • 4.13 MDIO User PHY Select Register 0 (USERPHYSEL0)

    78
  • 4.14 MDIO User Access Register 1 (USERACCESS1)

    79
  • 4.15 MDIO User PHY Select Register 1 (USERPHYSEL1)

    80
• 5 EMAC Port Registers

  81
  • 5.1 Introduction

    81
  • 5.2 Transmit Identification and Version Register (TXIDVER)

    85
  • 5.3 Transmit Control Register (TXCONTROL)

    86
  • 5.4 Transmit Teardown Register (TXTEARDOWN)

    87
  • 5.5 Receive Identification and Version Register (RXIDVER)

    88
  • 5.6 Receive Control Register (RXCONTROL)

    89
  • 5.7 Receive Teardown Register (RXTEARDOWN)

    90
  • 5.8 Transmit Interrupt Status (Unmasked) Register (TXINTSTATRAW)

    91
  • 5.9 Transmit Interrupt Status (Masked) Register (TXINTSTATMASKED)

    92
  • 5.10 Transmit Interrupt Mask Set Register (TXINTMASKSET)

    93
  • 5.11 Transmit Interrupt Mask Clear Register (TXINTMASKCLEAR)

    94
  • 5.12 MAC Input Vector Register (MACINVECTOR)

    95
  • 5.13 Receive Interrupt Status (Unmasked) Register (RXINTSTATRAW)

    96
  • 5.14 Receive Interrupt Status (Masked) Register (RXINTSTATMASKED)

    97
  • 5.15 Receive Interrupt Mask Set Register (RXINTMASKSET)

    98
  • 5.16 Receive Interrupt Mask Clear Register (RXINTMASKCLEAR)

    99
  • 5.17 MAC Interrupt Status (Unmasked) Register (MACINTSTATRAW)

    100
  • 5.18 MAC Interrupt Status (Masked) Register (MACINTSTATMASKED)

    101
  • 5.19 MAC Interrupt Mask Set Register (MACINTMASKSET)

    102
  • 5.20 MAC Interrupt Mask Clear Register (MACINTMASKCLEAR)

    103
  • 5.21 Receive Multicast/Broadcast/Promiscuous Channel Enable Register (RXMBPENABLE)

    104
  • 5.22 Receive Unicast Enable Set Register (RXUNICASTSET)

    106
  • 5.23 Receive Unicast Clear Register (RXUNICASTCLEAR)

    107
  • 5.24 Receive Maximum Length Register (RXMAXLEN)

    108
  • 5.25 Receive Buffer Offset Register (RXBUFFEROFFSET)

    109
  • 5.26 Receive Filter Low Priority Frame Threshold Register (RXFILTERLOWTHRESH)

    110
  • 5.27 Receive Channel 0-7 Flow Control Threshold Register (RXnFLOWTHRESH)

    111
  • 5.28 Receive Channel 0-7 Free Buffer Count Register (RXnFREEBUFFER)

    112
  • 5.29 MAC Control Register (MACCONTROL)

    113
  • 5.30 MAC Status Register (MACSTATUS)

    115
  • 5.31 Emulation Control Register (EMCONTROL)

    117
  • 5.32 FIFO Control Register (FIFOCONTROL)

    118
  • 5.33 MAC Configuration Register (MACCONFIG)

    119
  • 5.34 Soft Reset Register (SOFTRESET)

    120
  • 5.35 MAC Source Address Low Bytes Register (MACSRCADDRLO)

    121
  • 5.36 MAC Source Address High Bytes Register (MACSRCADDRHI)

    122
  • 5.37 MAC Hash Address Register 1 (MACHASH1)

    123
  • 5.38 MAC Hash Address Register 2 (MACHASH2)

    124
  • 5.39 Back Off Test Register (BOFFTEST)

    125
  • 5.40 Transmit Pacing Algorithm Test Register (TPACETEST)

    126
  • 5.41 Receive Pause Timer Register (RXPAUSE)

    127
  • 5.42 Transmit Pause Timer Register (TXPAUSE)

    128
  • 5.43 MAC Address Low Bytes Register (MACADDRLO)

    129
  • 5.44 MAC Address High Bytes Register (MACADDRHI)

    130
  • 5.45 MAC Index Register (MACINDEX)

    131
  • 5.46 Transmit Channel 0-7 DMA Head Descriptor Pointer Register (TXnHDP)

    132
  • 5.47 Receive Channel 0-7 DMA Head Descriptor Pointer Register (RXnHDP)

    133
  • 5.48 Transmit Channel 0-7 Completion Pointer Register (TXnCP)

    134
  • 5.49 Receive Channel 0-7 Completion Pointer Register (RXnCP)

    135
  • 5.50 Network Statistics Registers

    136
    • 5.50.1 Good Receive Frames Register (RXGOODFRAMES)

      136
    • 5.50.2 Broadcast Receive Frames Register (RXBCASTFRAMES)

      136
    • 5.50.3 Multicast Receive Frames Register (RXMCASTFRAMES)

      137
    • 5.50.4 Pause Receive Frames Register (RXPAUSEFRAMES)

      137
    • 5.50.5 Receive CRC Errors Register (RXCRCERRORS)

      137
    • 5.50.6 Receive Alignment/Code Errors Register (RXALIGNCODEERRORS)

      137
    • 5.50.7 Receive Oversized Frames Register (RXOVERSIZED)

      138
    • 5.50.8 Receive Jabber Frames Register (RXJABBER)

      138
    • 5.50.9 Receive Undersized Frames Register (RXUNDERSIZED)

      138
    • 5.50.10 Receive Frame Fragments Register (RXFRAGMENTS)

      138
    • 5.50.11 Filtered Receive Frames Register (RXFILTERED)

      139
    • 5.50.12 Receive QOS Filtered Frames Register (RXQOSFILTERED)

      139
    • 5.50.13 Receive Octet Frames Register (RXOCTETS)

      139
    • 5.50.14 Good Transmit Frames Register (TXGOODFRAMES)

      139
    • 5.50.15 Broadcast Transmit Frames Register (TXBCASTFRAMES)

      140
    • 5.50.16 Multicast Transmit Frames Register (TXMCASTFRAMES)

      140
    • 5.50.17 Pause Transmit Frames Register (TXPAUSEFRAMES)

      140
    • 5.50.18 Deferred Transmit Frames Register (TXDEFERRED)

      140
    • 5.50.19 Transmit Collision Frames Register (TXCOLLISION)

      140
    • 5.50.20 Transmit Single Collision Frames Register (TXSINGLECOLL)

      141
    • 5.50.21 Transmit Multiple Collision Frames Register (TXMULTICOLL)

      141
    • 5.50.22 Transmit Excessive Collision Frames Register (TXEXCESSIVECOLL)

      141
    • 5.50.23 Transmit Late Collision Frames Register (TXLATECOLL)

      141
    • 5.50.24 Transmit Underrun Error Register (TXUNDERRUN)

      141
    • 5.50.25 Transmit Carrier Sense Errors Register (TXCARRIERSENSE)

      142
    • 5.50.26 Transmit Octet Frames Register (TXOCTETS)

      142
    • 5.50.27 Transmit and Receive 64 Octet Frames Register (FRAME64)

      142
    • 5.50.28 Transmit and Receive 65 to 127 Octet Frames Register (FRAME65T127)

      142
    • 5.50.29 Transmit and Receive 128 to 255 Octet Frames Register (FRAME128T255)

      142
    • 5.50.30 Transmit and Receive 256 to 511 Octet Frames Register (FRAME256T511)

      143
    • 5.50.31 Transmit and Receive 512 to 1023 Octet Frames Register (FRAME512T1023)

      143
    • 5.50.32 Transmit and Receive 1024 to RXMAXLEN Octet Frames Register (FRAME1024TUP)

      143
    • 5.50.33 Network Octet Frames Register (NETOCTETS)

      143
    • 5.50.34 Receive FIFO or DMA Start of Frame Overruns Register (RXSOFOVERRUNS)

      144
    • 5.50.35 Receive FIFO or DMA Middle of Frame Overruns Register (RXMOFOVERRUNS)

      144
    • 5.50.36 Receive DMA Start of Frame and Middle of Frame Overruns Register (RXDMAOVERRUNS)

      144
• Appendix A Glossary

  145
• Appendix B Revision History

  147