用户手册目录Table of Contents3Preface101 Introduction111.1 Purpose of the Peripheral111.2 Features111.3 Functional Block Diagram121.4 Industry Standard(s) Compliance Statement132 EMAC Functional Architecture142.1 Clock Control142.1.1 MII Clocking142.1.2 RMII Clocking142.1.3 GMII Clocking142.1.4 RGMII Clocking152.2 Memory Map152.3 System Level Connections162.3.1 Media Independent Interface (MII) Connections162.3.2 Reduced Media Independent Interface (RMII) Connections182.3.3 Gigabit Media Independent Interface (GMII) Connections202.3.4 Reduced Gigabit Media Independent Interface (RGMII) Connections222.4 Ethernet Protocol Overview242.4.1 Ethernet Frame Format242.4.2 Multiple Access Protocol252.5 Programming Interface262.5.1 Packet Buffer Descriptors262.5.2 Transmit and Receive Descriptor Queues282.5.3 Transmit and Receive EMAC Interrupts292.5.4 Transmit Buffer Descriptor Format302.5.4.1 Next Descriptor Pointer312.5.4.2 Buffer Pointer312.5.4.3 Buffer Offset312.5.4.4 Buffer Length312.5.4.5 Packet Length312.5.4.6 Start of Packet (SOP) Flag312.5.4.7 End of Packet (EOP) Flag322.5.4.8 Ownership (OWNER) Flag322.5.4.9 End of Queue (EOQ) Flag322.5.4.10 Teardown Complete (TDOWNCMPLT) Flag322.5.4.11 Pass CRC (PASSCRC) Flag322.5.5 Receive Buffer Descriptor Format332.5.5.1 Next Descriptor Pointer342.5.5.2 Buffer Pointer342.5.5.3 Buffer Offset342.5.5.4 Buffer Length342.5.5.5 Packet Length342.5.5.6 Start of Packet (SOP) Flag352.5.5.7 End of Packet (EOP) Flag352.5.5.8 Ownership (OWNER) Flag352.5.5.9 End of Queue (EOQ) Flag352.5.5.10 Teardown Complete (TDOWNCMPLT) Flag352.5.5.11 Pass CRC (PASSCRC) Flag352.5.5.12 Jabber Flag352.5.5.13 Oversize Flag352.5.5.14 Fragment Flag362.5.5.15 Undersized Flag362.5.5.16 Control Flag362.5.5.17 Overrun Flag362.5.5.18 Code Error (CODEERROR) Flag362.5.5.19 Alignment Error (ALIGNERROR) Flag362.5.5.20 CRC Error (CRCERROR) Flag362.5.5.21 No Match (NOMATCH) Flag362.6 EMAC Control Module372.6.1 Internal Memory372.6.2 Bus Arbiter372.6.3 Interrupt Control382.7 Management Data Input/Output (MDIO) Module382.7.1 MDIO Module Components382.7.1.1 MDIO Clock Generator392.7.1.2 Global PHY Detection and Link State Monitoring392.7.1.3 Active PHY Monitoring392.7.1.4 PHY Register User Access392.7.2 MDIO Module Operational Overview402.7.2.1 Initializing the MDIO Module402.7.2.2 Writing Data to a PHY Register412.7.2.3 Reading Data From a PHY Register412.7.2.4 Example of MDIO Register Access Code412.8 EMAC Module432.8.1 EMAC Module Components432.8.1.1 Receive DMA Engine432.8.1.2 Receive FIFO432.8.1.3 MAC Receiver442.8.1.4 Receive Address442.8.1.5 Transmit DMA Engine442.8.1.6 Transmit FIFO442.8.1.7 MAC Transmitter442.8.1.8 Statistics Logic442.8.1.9 State RAM442.8.1.10 EMAC Interrupt Controller442.8.1.11 Control Registers and Logic442.8.1.12 Clock and Reset Logic452.8.2 EMAC Module Operational Overview452.9 Media Independent Interfaces462.9.1 Data Reception462.9.1.1 Receive Control462.9.1.2 Receive Inter-Frame Interval462.9.1.3 Receive Flow Control462.9.1.4 Collision-Based Receive Buffer Flow Control472.9.1.5 IEEE 802.3X Based Receive Buffer Flow Control472.9.2 Data Transmission482.9.2.1 Transmit Control482.9.2.2 CRC Insertion482.9.2.3 Adaptive Performance Optimization (APO)482.9.2.4 Interpacket-Gap (IPG) Enforcement482.9.2.5 Back Off482.9.2.6 Transmit Flow Control492.9.2.7 Speed, Duplex, and Pause Frame Support492.10 Packet Receive Operation502.10.1 Receive DMA Host Configuration502.10.2 Receive Channel Enabling502.10.3 Receive Channel Addressing512.10.4 Hardware Receive QOS Support512.10.5 Host Free Buffer Tracking522.10.6 Receive Channel Teardown522.10.7 Receive Frame Classification522.10.8 Promiscuous Receive Mode532.10.9 Receive Overrun542.11 Packet Transmit Operation552.11.1 Transmit DMA Host Configuration552.11.2 Transmit Channel Teardown552.12 Receive and Transmit Latency552.13 Transfer Node Priority562.14 Reset Considerations562.14.1 Software Reset Considerations562.14.2 Hardware Reset Considerations562.15 Initialization572.15.1 Enabling the EMAC/MDIO Peripheral572.15.2 EMAC Control Module Initialization572.15.3 MDIO Module Initialization582.15.4 EMAC Module Initialization592.16 Interrupt Support602.16.1 EMAC Module Interrupt Events and Requests602.16.1.1 Transmit Packet Completion Interrupts602.16.1.2 Receive Packet Completion Interrupts612.16.1.3 Statistics Interrupt612.16.1.4 Host Error Interrupt622.16.2 MDIO Module Interrupt Events and Requests622.16.2.1 Link Change Interrupt622.16.2.2 User Access Completion Interrupt622.16.3 Proper Interrupt Processing632.16.4 Interrupt Multiplexing632.17 Power Management632.18 Emulation Considerations633 EMAC Control Module Registers643.1 Introduction643.2 EMAC Control Module Interrupt Control Register (EWCTL)643.3 EMAC Control Module Interrupt Timer Count Register (EWINTTCNT)654 MDIO Registers664.1 Introduction664.2 MDIO Version Register (VERSION)674.3 MDIO Control Register (CONTROL)684.4 PHY Acknowledge Status Register (ALIVE)694.5 PHY Link Status Register (LINK)704.6 MDIO Link Status Change Interrupt (Unmasked) Register (LINKINTRAW)714.7 MDIO Link Status Change Interrupt (Masked) Register (LINKINTMASKED)724.8 MDIO User Command Complete Interrupt (Unmasked) Register (USERINTRAW)734.9 MDIO User Command Complete Interrupt (Masked) Register (USERINTMASKED)744.10 MDIO User Command Complete Interrupt Mask Set Register (USERINTMASKSET)754.11 MDIO User Command Complete Interrupt Mask Clear Register (USERINTMASKCLEAR)764.12 MDIO User Access Register 0 (USERACCESS0)774.13 MDIO User PHY Select Register 0 (USERPHYSEL0)784.14 MDIO User Access Register 1 (USERACCESS1)794.15 MDIO User PHY Select Register 1 (USERPHYSEL1)805 EMAC Port Registers815.1 Introduction815.2 Transmit Identification and Version Register (TXIDVER)855.3 Transmit Control Register (TXCONTROL)865.4 Transmit Teardown Register (TXTEARDOWN)875.5 Receive Identification and Version Register (RXIDVER)885.6 Receive Control Register (RXCONTROL)895.7 Receive Teardown Register (RXTEARDOWN)905.8 Transmit Interrupt Status (Unmasked) Register (TXINTSTATRAW)915.9 Transmit Interrupt Status (Masked) Register (TXINTSTATMASKED)925.10 Transmit Interrupt Mask Set Register (TXINTMASKSET)935.11 Transmit Interrupt Mask Clear Register (TXINTMASKCLEAR)945.12 MAC Input Vector Register (MACINVECTOR)955.13 Receive Interrupt Status (Unmasked) Register (RXINTSTATRAW)965.14 Receive Interrupt Status (Masked) Register (RXINTSTATMASKED)975.15 Receive Interrupt Mask Set Register (RXINTMASKSET)985.16 Receive Interrupt Mask Clear Register (RXINTMASKCLEAR)995.17 MAC Interrupt Status (Unmasked) Register (MACINTSTATRAW)1005.18 MAC Interrupt Status (Masked) Register (MACINTSTATMASKED)1015.19 MAC Interrupt Mask Set Register (MACINTMASKSET)1025.20 MAC Interrupt Mask Clear Register (MACINTMASKCLEAR)1035.21 Receive Multicast/Broadcast/Promiscuous Channel Enable Register (RXMBPENABLE)1045.22 Receive Unicast Enable Set Register (RXUNICASTSET)1065.23 Receive Unicast Clear Register (RXUNICASTCLEAR)1075.24 Receive Maximum Length Register (RXMAXLEN)1085.25 Receive Buffer Offset Register (RXBUFFEROFFSET)1095.26 Receive Filter Low Priority Frame Threshold Register (RXFILTERLOWTHRESH)1105.27 Receive Channel 0-7 Flow Control Threshold Register (RXnFLOWTHRESH)1115.28 Receive Channel 0-7 Free Buffer Count Register (RXnFREEBUFFER)1125.29 MAC Control Register (MACCONTROL)1135.30 MAC Status Register (MACSTATUS)1155.31 Emulation Control Register (EMCONTROL)1175.32 FIFO Control Register (FIFOCONTROL)1185.33 MAC Configuration Register (MACCONFIG)1195.34 Soft Reset Register (SOFTRESET)1205.35 MAC Source Address Low Bytes Register (MACSRCADDRLO)1215.36 MAC Source Address High Bytes Register (MACSRCADDRHI)1225.37 MAC Hash Address Register 1 (MACHASH1)1235.38 MAC Hash Address Register 2 (MACHASH2)1245.39 Back Off Test Register (BOFFTEST)1255.40 Transmit Pacing Algorithm Test Register (TPACETEST)1265.41 Receive Pause Timer Register (RXPAUSE)1275.42 Transmit Pause Timer Register (TXPAUSE)1285.43 MAC Address Low Bytes Register (MACADDRLO)1295.44 MAC Address High Bytes Register (MACADDRHI)1305.45 MAC Index Register (MACINDEX)1315.46 Transmit Channel 0-7 DMA Head Descriptor Pointer Register (TXnHDP)1325.47 Receive Channel 0-7 DMA Head Descriptor Pointer Register (RXnHDP)1335.48 Transmit Channel 0-7 Completion Pointer Register (TXnCP)1345.49 Receive Channel 0-7 Completion Pointer Register (RXnCP)1355.50 Network Statistics Registers1365.50.1 Good Receive Frames Register (RXGOODFRAMES)1365.50.2 Broadcast Receive Frames Register (RXBCASTFRAMES)1365.50.3 Multicast Receive Frames Register (RXMCASTFRAMES)1375.50.4 Pause Receive Frames Register (RXPAUSEFRAMES)1375.50.5 Receive CRC Errors Register (RXCRCERRORS)1375.50.6 Receive Alignment/Code Errors Register (RXALIGNCODEERRORS)1375.50.7 Receive Oversized Frames Register (RXOVERSIZED)1385.50.8 Receive Jabber Frames Register (RXJABBER)1385.50.9 Receive Undersized Frames Register (RXUNDERSIZED)1385.50.10 Receive Frame Fragments Register (RXFRAGMENTS)1385.50.11 Filtered Receive Frames Register (RXFILTERED)1395.50.12 Receive QOS Filtered Frames Register (RXQOSFILTERED)1395.50.13 Receive Octet Frames Register (RXOCTETS)1395.50.14 Good Transmit Frames Register (TXGOODFRAMES)1395.50.15 Broadcast Transmit Frames Register (TXBCASTFRAMES)1405.50.16 Multicast Transmit Frames Register (TXMCASTFRAMES)1405.50.17 Pause Transmit Frames Register (TXPAUSEFRAMES)1405.50.18 Deferred Transmit Frames Register (TXDEFERRED)1405.50.19 Transmit Collision Frames Register (TXCOLLISION)1405.50.20 Transmit Single Collision Frames Register (TXSINGLECOLL)1415.50.21 Transmit Multiple Collision Frames Register (TXMULTICOLL)1415.50.22 Transmit Excessive Collision Frames Register (TXEXCESSIVECOLL)1415.50.23 Transmit Late Collision Frames Register (TXLATECOLL)1415.50.24 Transmit Underrun Error Register (TXUNDERRUN)1415.50.25 Transmit Carrier Sense Errors Register (TXCARRIERSENSE)1425.50.26 Transmit Octet Frames Register (TXOCTETS)1425.50.27 Transmit and Receive 64 Octet Frames Register (FRAME64)1425.50.28 Transmit and Receive 65 to 127 Octet Frames Register (FRAME65T127)1425.50.29 Transmit and Receive 128 to 255 Octet Frames Register (FRAME128T255)1425.50.30 Transmit and Receive 256 to 511 Octet Frames Register (FRAME256T511)1435.50.31 Transmit and Receive 512 to 1023 Octet Frames Register (FRAME512T1023)1435.50.32 Transmit and Receive 1024 to RXMAXLEN Octet Frames Register (FRAME1024TUP)1435.50.33 Network Octet Frames Register (NETOCTETS)1435.50.34 Receive FIFO or DMA Start of Frame Overruns Register (RXSOFOVERRUNS)1445.50.35 Receive FIFO or DMA Middle of Frame Overruns Register (RXMOFOVERRUNS)1445.50.36 Receive DMA Start of Frame and Middle of Frame Overruns Register (RXDMAOVERRUNS)144Appendix A Glossary145Appendix B Revision History147文件大小: 992.4 KB页数: 148Language: English打开用户手册