Manuale UtenteSommarioTable of Contents3Preface131 Overview161.1 Video Port171.2 Video Port FIFO191.2.1 EDMA Interface191.2.2 Video Capture FIFO Configurations201.2.3 Video Display FIFO Configurations231.3 Video Port Registers251.4 Video Port Pin Mapping261.4.1 VDIN Bus Usage for Capture Modes271.4.2 VDOUT Data Bus Usage for Display Modes281.5 Video Port Pin Multiplexing281.6 VideoPort Clocking282 Video Port292.1 Reset Operation302.1.1 Power-On Reset302.1.2 Peripheral Bus Reset302.1.3 Software Port Reset302.1.4 Capture Channel Reset312.1.5 Display Channel Reset312.2 Interrupt Operation312.3 EDMA Operation322.3.1 Capture EDMA Event Generation322.3.2 Display EDMA Event Generation332.3.3 EDMA Size and Threshold Restrictions332.3.4 EDMA Interface Operation342.4 Video Port Control Registers342.4.1 Video Port Control Register (VPCTL)352.4.2 Video Port Status Register (VPSTAT)372.4.3 Video Port Interrupt Enable Register (VPIE)382.4.4 Video Port Interrupt Status Register (VPIS)403 Video Capture Port453.1 Video Capture Mode Selection463.2 BT.656 Video Capture Mode463.2.1 BT.656 Capture Channels463.2.2 BT.656 Timing Reference Codes463.2.3 BT.656 Image Window and Capture483.2.4 BT.656 Data Sampling493.2.5 BT.656 FIFO Packing493.3 Y/C Video Capture Mode503.3.1 Y/C Capture Channels503.3.2 Y/C Timing Reference Codes503.3.3 Y/C Image Window and Capture503.3.4 Y/C FIFO Packing513.4 BT.656 and Y/C Mode Field and Frame Operation513.4.1 Capture Determination and Notification523.4.2 Vertical Synchronization533.4.3 Horizontal Synchronization553.4.4 Field Identification563.4.5 Short and Long Field Detect573.5 Video Input Filtering573.5.1 Input Filter Modes583.5.2 Chrominance Re-sampling Operation583.5.3 Scaling Operation583.5.4 Edge Pixel Replication593.6 Ancillary Data Capture603.6.1 Horizontal Ancillary (HANC) Data Capture613.6.2 Vertical Ancillary (VANC) Data Capture613.7 Raw Data Capture Mode613.7.1 Raw Data Capture Notification613.7.2 Raw Data FIFO Packing623.8 TCI Capture Mode633.8.1 TCI Capture Features633.8.2 TCI Data Capture633.8.3 TCI Capture Error Detection643.8.4 Synchronizing the System Clock643.8.5 TCI Data Capture Notification653.8.6 Writing to the FIFO663.8.7 Reading from the FIFO663.9 Capture Line Boundary Conditions673.10 Capturing Video in BT.656 or Y/C Mode673.10.1 Handling FIFO Overrun in BT.656 or Y/C Mode683.11 Capturing Video in Raw Data Mode683.11.1 Handling FIFO Overrun Condition in Raw Data Mode693.12 Capturing Data in TCI Capture Mode693.12.1 Handling FIFO Overrun Condition in TCI Capture Mode703.13 Video Capture Registers703.13.1 Video Capture Channel x Status Register (VCASTAT, VCBSTAT)713.13.2 Video Capture Channel A Control Register (VCACTL)723.13.3 Video Capture Channel x Field 1 Start Register (VCxSTRT1)753.13.4 Video Capture Channel x Field 1 Stop Register (VCxSTOP1)763.13.5 Video Capture Channel x Field 2 Start Register (VCxSTRT2)773.13.6 Video Capture Channel x Field 2 Stop Register (VCxSTOP2)783.13.7 Video Capture Channel x Vertical Interrupt Register (VCxVINT)793.13.8 Video Capture Channel x Threshold Register (VCATHRLD, VCBTHRLD)803.13.9 Video Capture Channel x Event Count Register (VCxEVTCT)813.13.10 Video Capture Channel B Control Register (VCBCTL)813.13.11 TCI Capture Control Register (TCICTL)843.13.12 TCI Clock Initialization LSB Register (TCICLKINITL)853.13.13 TCI Clock Initialization MSB Register (TCICLKINITM)863.13.14 TCI System Time Clock LSB Register (TCISTCLKL)863.13.15 TCI System Time Clock MSB Register (TCISTCLKM)873.13.16 TCI System Time Clock Compare LSB Register (TCISTCMPL)883.13.17 TCI System Time Clock Compare MSB Register (TCISTCMPM)883.13.18 TCI System Time Clock Compare Mask LSB Register (TCISTMSKL)893.13.19 TCI System Time Clock Compare Mask MSB Register (TCISTMSKM)893.13.20 TCI System Time Clock Ticks Interrupt Register (TCITICKS)903.14 Video Capture FIFO Registers914 Video Display Port924.1 Video Display Mode Selection934.1.1 Image Timing934.1.2 Video Display Counters964.1.3 Sync Signal Generation984.1.4 External Sync Operation984.1.5 Port Sync Operation984.2 BT.656 Video Display Mode984.2.1 Display Timing Reference Codes994.2.2 Blanking Codes1014.2.3 BT.656 Image Display1014.2.4 BT.656 FIFO Unpacking1014.3 Y/C Video Display Mode1024.3.1 Y/C Display Timing Reference Codes1024.3.2 Y/C Blanking Codes1024.3.3 Y/C Image Display1024.3.4 Y/C FIFO Unpacking1034.4 Video Output Filtering1034.4.1 Output Filter Modes1034.4.2 Chrominance Re-sampling Operation1044.4.3 Scaling Operation1044.4.4 Edge Pixel Replication1054.5 Ancillary Data Display1064.5.1 Horizontal Ancillary (HANC) Data Display1064.5.2 Vertical Ancillary (VANC) Data Display1064.6 Raw Data Display Mode1064.6.1 Raw Mode RGB Output Support1074.6.2 Raw Data FIFO Unpacking1074.7 Video Display Field and Frame Operation1084.7.1 Display Determination and Notification1084.7.2 Video Display Event Generation1094.8 Display Line Boundary Conditions1094.9 Display Timing Examples1104.9.1 Interlaced BT.656 Timing Example1104.9.2 Interlaced Raw Display Example1134.9.3 Y/C Progressive Display Example1164.10 Displaying Video in BT.656 or Y/C Mode1194.11 Displaying Video in Raw Data Mode1204.11.1 Handling Under-run Condition of the Display FIFO1214.12 Video Display Registers1224.12.1 Video Display Status Register (VDSTAT)1224.12.2 Video Display Control Register (VDCTL)1234.12.3 Video Display Frame Size Register (VDFRMSZ)1274.12.4 Video Display Horizontal Blanking Register (VDHBLNK)1274.12.5 Video Display Field 1 Vertical Blanking Start Register (VDVBLKS1)1284.12.6 Video Display Field 1 Vertical Blanking End Register (VDVBLKE1)1294.12.7 Video Display Field 2 Vertical Blanking Start Register (VDVBLKS2)1304.12.8 Video Display Field 2 Vertical Blanking End Register (VDVBLKE2)1314.12.9 Video Display Field 1 Image Offset Register (VDIMGOFF1)1324.12.10 Video Display Field 1 Image Size Register (VDIMGSZ1)1334.12.11 Video Display Field 2 Image Offset Register (VDIMGOFF2)1344.12.12 Video Display Field 2 Image Size Register (VDIMGSZ2)1354.12.13 Video Display Field 1 Timing Register (VDFLDT1)1354.12.14 Video Display Field 2 Timing Register (VDFLDT2)1364.12.15 Video Display Threshold Register (VDTHRLD)1374.12.16 Video Display Horizontal Synchronization Register (VDHSYNC)1384.12.17 Video Display Field 1 Vertical Synchronization Start Register (VDVSYNS1)1384.12.18 Video Display Field 1 Vertical Synchronization End Register (VDVSYNE1)1394.12.19 Video Display Field 2 Vertical Synchronization Start Register (VDVSYNS2)1404.12.20 Video Display Field 2 Vertical Synchronization End Register (VDVSYNE2)1404.12.21 Video Display Counter Reload Register (VDRELOAD)1414.12.22 Video Display Event Register (VDDISPEVT)1424.12.23 Video Display Clipping Register (VDCLIP)1424.12.24 Video Display Default Display Value Register (VDDEFVAL)1434.12.25 Video Display Vertical Interrupt Register (VDVINT)1444.12.26 Video Display Field Bit Register (VDFBIT)1454.12.27 Video Display Field 1 Vertical Blanking Bit Register (VDVBIT1)1464.12.28 Video Display Field 2 Vertical Blanking Bit Register (VDVBIT2)1474.13 Video Display Registers Recommended Values1484.14 Video Display FIFO Registers1495 General-Purpose I/O Operation1505.1 GPIO Registers1515.1.1 Video Port Peripheral Identification Register (VPPID)1525.1.2 Video Port Peripheral Control Register (PCR)1535.1.3 Video Port Pin Function Register (PFUNC)1545.1.4 Video Port Pin Direction Register (PDIR)1565.1.5 Video Port Pin Data Input Register (PDIN)1585.1.6 Video Port Pin Data Output Register (PDOUT)1595.1.7 Video Port Pin Data Set Register (PDSET)1615.1.8 Video Port Pin Data Clear Register (PDCLR)1625.1.9 Video Port Pin Interrupt Enable Register (PIEN)1635.1.10 Video Port Pin Interrupt Polarity Register (PIPOL)1645.1.11 Video Port Pin Interrupt Status Register (PISTAT)1655.1.12 Video Port Pin Interrupt Clear Register (PICLR)1666 VCXO Interpolated Control Port1676.1 Overview1686.2 Interface1686.3 Operational Details1696.4 Enabling VIC Port1706.5 VIC Port Registers1706.5.1 VIC Control Register (VICCTL)1716.5.2 VIC Input Register (VICIN)1726.5.3 VIC Clock Divider Register (VICDIV)173Dimensioni: 1,57 MBPagine: 174Language: EnglishApri il manuale