Hitachi H8/3692 ユーザーズマニュアル
Rev. 1.0, 07/01, page 143 of 372
OS3 and OS2 select the output level for compare match B. OS1 and OS0 select the output level
for compare match A. The two output levels can be controlled independently. After a reset, the
timer output is 0 until the first compare match.
for compare match A. The two output levels can be controlled independently. After a reset, the
timer output is 0 until the first compare match.
11.3.5
Timer Control Register V1(TCRV1)
TCRV1 is an 8-bit read/write register that selects the edge at the TRGV pin, enables TRGV input,
and selects the clock input to TCNTV.
and selects the clock input to TCNTV.
Bit
Bit Name
Initial Value R/W
Description
7
6
5
−
−
−
−
−
1
1
1
−
−
−
−
−
Reserved
These bits are always read as 1 and cannot be modified.
4
3
TVEG1
TVEG0
0
0
R/W
R/W
TRGV Input Edge Select
These bits select the TRGV input edge.
00: TRGV trigger input is disabled
01: Rising edge is selected
10: Falling edge is selected
11: Rising and falling edges are both selected
2
TRGE
0
R/W
TRGV Input Enable
This bit enables starting counting-up TCNTV by the input of
edges selected by TVEG1 and TVEG0.
edges selected by TVEG1 and TVEG0.
0: This bit disables starting counting-up TCNTV by the
input of the TRGV pin and halting counting-up TCNTV
when TCNTV is cleared by a compare match.
when TCNTV is cleared by a compare match.
1: This bit enables starting counting-up TCNTV by the input
of the TRGV pin and halting counting-up TCNTV when
TCNTV is cleared by a compare match.
TCNTV is cleared by a compare match.
1
−
1
−
Reserved
This bit is always read as 1 and cannot be modified.
0
ICKS0
0
R/W
Internal Clock Select 0
This bit selects clock signals to input to TCNTV in
combination with CKS2 to CKS0 in TCRV0.
combination with CKS2 to CKS0 in TCRV0.
Refer to table 11-2.