Hitachi H8/3692 ユーザーズマニュアル

Rev. 1.0, 07/01, Page 

vii

 of 

xxiv

Contents

Section 1   Overview........................................................................................................... ......... 1
1.1

Overview.................................................................................................................... ....... 1

1.2

Internal Block Diagram..................................................................................................... 2

1.3

Pin Arrangement ............................................................................................................. .. 3

1.4

Pin Functions ............................................................................................................... ..... 5

Section 2   CPU................................................................................................... 7

2.1

Address Space and Memory Map ..................................................................................... 8

2.2

Register Configuration ...................................................................................................... 10
2.2.1

General Registers ................................................................................................. 11

2.2.2

Program Counter (PC) ......................................................................................... 12

2.2.3

Condition-Code Register (CCR) .......................................................................... 12

2.3

Data Formats ..................................................................................................................... 14
2.3.1

General Register Data Formats ............................................................................ 14

2.3.2

Memory Data Formats ......................................................................................... 16

2.4

Instruction Set ................................................................................................................... 17
2.4.1

Table of Instructions Classified by Function ....................................................... 17

2.4.2

Basic Instruction Formats .................................................................................... 26

2.5

Addressing Modesand Effective Address Calculation ...................................................... 28
2.5.1

Addressing Modes ............................................................................................... 28

2.5.2

Effective Address Calculation ............................................................................. 30

2.6

Basic Bus Cycle ................................................................................................................ 33
2.6.1

Access to On-Chip Memory (RAM, ROM)......................................................... 33

2.6.2

On-Chip Peripheral Modules ............................................................................... 34

2.7

CPU States ........................................................................................................................ 35

2.8

Usage Notes ...................................................................................................................... 36
2.8.1

Notes on Data Access to Empty Areas ................................................................ 36

2.8.2

EEPMOV Instruction........................................................................................... 36

2.8.3

Bit Manipulation Instruction ................................................................................ 36

Section 3   Exception Handling .......................................................................... 43

3.1

Exception Sources and Vector Address ............................................................................ 43

3.2

Register Descriptions ........................................................................................................ 45
3.2.1

Interrupt Edge Select Register 1(IEGR1) ............................................................ 45

3.2.2

Interrupt Edge Select Register 2(IEGR2) ............................................................ 46

3.2.3

Interrupt Enable Register 1(IENR1) .................................................................... 47

3.2.4

Interrupt Flag Register 1(IRR1) ........................................................................... 48

3.2.5

Wakeup Interrupt Flag Register(IWPR) .............................................................. 49

3.3

Reset ................................................................................................................................. 50

3.4

Interrupt Exception Handling............................................................................................ 50