Intel N450 AU80610004653AA ユーザーズマニュアル
製品コード
AU80610004653AA
Datasheet
61
Power Management
•
Deep Sleep exit: the system clock chip must start toggling BCLK within 10 BCLK
periods within DPSLP# de-assertion.
periods within DPSLP# de-assertion.
5.2.5.4
Deeper Sleep State
The Deeper Sleep state is similar to the Deep Sleep state but further reduces core
voltage levels. One of the potential lower core voltage levels is achieved by entering the
base Deeper Sleep state. The Deeper Sleep state is entered through assertion of the
DPRSTP# pin while in the Deep Sleep state.
voltage levels. One of the potential lower core voltage levels is achieved by entering the
base Deeper Sleep state. The Deeper Sleep state is entered through assertion of the
DPRSTP# pin while in the Deep Sleep state.
In response to entering Deeper Sleep, the processor drives the VID code corresponding
to the Deeper Sleep core voltage on the VID [6:0] pins.
to the Deeper Sleep core voltage on the VID [6:0] pins.
Exit from Deeper Sleep is initiated by DPRSTP# de-assertion when the core requests a
package state other than C4 or the core requests a processor performance state other
than the lowest operating point.
package state other than C4 or the core requests a processor performance state other
than the lowest operating point.
5.2.5.5
Extended Low-Power States
Extended low-power states (C1E, C2E, C4E) optimize for power by forcibly reducing the
performance state of the processor when it enters a package low-power state. Instead
of directly transitioning into the package low-power state, the extended low-power
state first reduces the performance state of the processor by performing an Enhanced
Intel
performance state of the processor when it enters a package low-power state. Instead
of directly transitioning into the package low-power state, the extended low-power
state first reduces the performance state of the processor by performing an Enhanced
Intel
®
SpeedStep Technology transition down to the lowest operating point. Upon
receiving a break event from the package low-power state, control will be returned to
software while an Enhanced Intel
software while an Enhanced Intel
®
SpeedStep Technology transition up to the initial
operating point occurs. The advantage of this feature is that it significantly reduces
leakage while in the package low power states. Also, long-term reliability may not
be assured if the Extended Low-Power States are not enabled.
leakage while in the package low power states. Also, long-term reliability may not
be assured if the Extended Low-Power States are not enabled.
The processor implements two software interfaces for requesting extended package
low-power states: MWAIT instruction extensions with sub-state hints and via BIOS by
configuring IA32_MISC_ENABLES MSR bits to automatically promote package low-
power states to extended package low-power states.
low-power states: MWAIT instruction extensions with sub-state hints and via BIOS by
configuring IA32_MISC_ENABLES MSR bits to automatically promote package low-
power states to extended package low-power states.
Extended Stop-Grant and Extended Deeper Sleep must be enabled via the
BIOS for the processor to remain within specification. Not complying to this
guideline may affect the long-term reliability of the processor.
BIOS for the processor to remain within specification. Not complying to this
guideline may affect the long-term reliability of the processor.
Enhanced Intel
®
SpeedStep Technology transitions are multi-step processes that
require clocked control. These transitions cannot occur when the processor is in the
Sleep or Deep Sleep package low-power states since processor clocks are not active in
these states. Extended Deeper Sleep is an exception to this rule when the Hard C4E
configuration is enabled in the IA32_MISC_ENABLES MSR. This Extended Deeper Sleep
state configuration will lower core voltage to the Deeper Sleep level while in Deeper
Sleep and, upon exit, will automatically transition to the lowest operating voltage and
frequency to reduce snoop service latency.
Sleep or Deep Sleep package low-power states since processor clocks are not active in
these states. Extended Deeper Sleep is an exception to this rule when the Hard C4E
configuration is enabled in the IA32_MISC_ENABLES MSR. This Extended Deeper Sleep
state configuration will lower core voltage to the Deeper Sleep level while in Deeper
Sleep and, upon exit, will automatically transition to the lowest operating voltage and
frequency to reduce snoop service latency.