Freescale Semiconductor MPC5200B ユーザーズマニュアル

4-2

Freescale Semiconductor

External SRESET is an open drain signal. SRESET requires an external pull-up. Assertion of SRESET causes assertion of the internal soft 
reset. Internal soft reset is actually an interrupt that takes the same exception vector as HRESET. In particular, this means that SRESET cannot 
abort a hung XLB operation, and no device should use SRESET in a way that interferes with any bus operation in progress.

SRESET can also be asserted by internal sources. When SRESET is asserted internally, external SRESET is also asserted.

Sources of soft reset:

•

PORRESET, HRESET, or SRESET external pins asserted

•

Soft reset bit in Clock Distribution Module (CDM) register asserted by processor

•

Soft reset asserted by debug module

PORRESET must remain asserted for at least 100

µs after all power supplies and the system oscillator input are stable and operating within 

specs. Following deassertion of power-on reset, HRESET and SRESET remain low for 4096 reference clock cycles.

PORRESET is asserted

Power-On Reset

Internal or External

SRESET is asserted

Internal or External

HRESET is asserted 

No Reset signals
recognized for 2
reference clock cycles

Assert internal and external
HRESET for 4096
reference clock cycles

PORRESET is negated and

Reset configuration is latched 

Assert internal and external
HRESET and SRESET
Sample configuration from
RST_CONFIG[15:0]
Power becomes stable

APLLs Lock

HRESET

Reset Hold

Wait 

Additional HRESET, SRESET Recognized

Sample configuration from
RST_CONFIG[15:0]