Freescale Semiconductor MPC5200B ユーザーズマニュアル
Other Resets
MPC5200B Users Guide, Rev. 1
Freescale Semiconductor
4-3
Figure 4-2. PORRESET Assertion
When external HRESET is asserted, internal reset logic catches the reset signal held low and asserts internal hard and soft resets for 4096
reference clock cycles. The external reset signal must be held low for at least 4 reference clock cycles (must catch 4 rising edges of reference
clock) to be recognized and assert the internal reset signals.
reference clock cycles. The external reset signal must be held low for at least 4 reference clock cycles (must catch 4 rising edges of reference
clock) to be recognized and assert the internal reset signals.
Figure 4-3. Internal Hard Reset vs External HRESET Assertion
The Clock Distribution Module contains a register that can be written by the microprocessor to assert soft reset. Writing the SRESET bit in
this register to zero causes external SRESET and internal soft reset to be asserted.
this register to zero causes external SRESET and internal soft reset to be asserted.
4.5
Other Resets
MPC5200B has four other reset signals. These signals are specific to certain peripheral modules and are controlled in the context of that
module, not globally.
module, not globally.
.
Table 4-1. Module Specific Reset Signals
Definition
PCI_RESET
PCI bus reset output. Generated by processor write to a PCI register.
AC97_1_RES
AC97 reset output. Generated from the AC97 PSC1 module.
AC97_2_RES
AC97 reset output. Generated from the AC97 PSC2 module.
PORRESET
SRESET
HRESET
4096 ref cycles
≥100 us
SYS_XTAL
All Power
Supplies
1 edge
3 edges
2 edges
4096 ref cycles
Internal
4
Reference clock
HRESET
Reset