Freescale Semiconductor MPC5200B ユーザーズマニュアル

Freescale Semiconductor

7-19

 

msb  0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

R

Reserved

MEa

W

RESET:

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31 lsb

R

MEa

W

RESET:

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0:14

—

Reserved

—

MEa[x]

This register provides a way for software to emulate the assertion of a particular Main/SIU 
interrupt. The actual interrupt is the OR or the normal interrupt source and each of these test 
register bits. The order is exactly the same as the MSa in

ICTL Main Interrupt Status All Register. 

The MEa[x] bits ARE masked by the Main_Mask setting, so they operate as

much as possible as the real interrupt source. Even the IRQ sources, which may be 
programmed as edge sensitive, will react just like the pin when emulated here with test bit 
assertion/negation. One exception is LO-int, which if asserted here, will NOT create a 
corresponding Peripheral Status indication.

If relying on MEa [x] assertion/negation to emulate and test an ISR routine it is

important to disable all source modules so that real source interrupts will not disturb

the test generated interrupt.

15

MEa0

Slice_Timer 1 (SMI interrupt only)

16

MEa1

IRQ[1] input pin

17

MEa2

IRQ[2] input pin

18

MEa3

IRQ[3] input pin

19

MEa4

LO_int (some Peripheral source)

20

MEa5

RTC_periodic interrupt

21

MEa6

RTC_stopwatch interrupt

22

MEa7

GPIO std interrupt

23

MEa8

GPIO WakeUp interrupt

24

MEa9

TMR0 interrupt

25

MEa10

TMR1 interrupt

26

MEa11

TMR2 interrupt

27

MEa12

TMR3 interrupt

28

MEa13

TMR4 interrupt

29

MEa14

TMR5 interrupt

30

MEa15

TMR6 interrupt

31

MEa16

TMR7 interrupt