Freescale Semiconductor MPC5200B ユーザーズマニュアル

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MPC5200B Users Guide, Rev. 1
7-20
Freescale Semiconductor
Interrupt Controller
7.2.4.15
ICTL Peripheral Interrupt Emulation All Register—MBAR + 0x0544
 
Table 7-18. ICTL Peripheral Interrupt Emulation All Register
msb  0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
Reserved
PEa
W
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31 lsb
R
PEa
Reserved
PEa21
W
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bits
Name
Description
0:7
Reserved
PEa[x]
This register provides a way for software to emulate the assertion of a particular Peripheral 
interrupt. The actual interrupt is the OR or the normal interrupt source and each of these test 
register bits. The order is exactly the same as the PSa in ICTL Peripheral Interrupt Status All 
Register. The PEa[x] bits ARE masked by the Per_Mask setting, so they operate as much as 
possible as the real interrupt source. Test assertion of a Periperhal source will cause HI-int 
or LO-int indications which will be reflected in the Main or Critical status registers. If relying 
on PEa[x] assertion/negation to emulate and test an ISR routine it is important to disable all 
source modules so that real source interrupts will not disturb the test generated interrupt.
8
PEa23
BestComm LocalPlus
9
PEa22
BDLC
10
PEa0
BestComm interrupt source
11
PEa1
PSC1
12
PEa2
PSC2
13
PEa3
PSC3
14
PEa4
PSC6
15
PEa5
Ethernet
16
PEa6
USB
17
PEa7
ATA
18
PEa8
PCI Control module
19
PEa9
PCI SC Initiator Rx
20
PEa10
PCI SC Initiator Tx
21
PEa11
PSC4
22
PEa12
PSC5
23
PEa13
SPI modf
24
PEa14
SPI spif
25
PEa15
I
2
C1
26
PEa16
I
2
C2