Freescale Semiconductor MPC5200B ユーザーズマニュアル
Functional Description
MPC5200B Users Guide, Rev. 1
Freescale Semiconductor
8-17
modulo 8 boundary within the modulo 32 range; the address “wraps” from the highest address to the lowest address of the range if the starting
address is not aligned at the beginning of the range. No data is masked during a burst.
address is not aligned at the beginning of the range. No data is masked during a burst.
The beat address order of the XL bus is sequential. Based on the start address issued by the internal master, the address order of the 4 XLD
beats in a burst transfer is one of the following:
beats in a burst transfer is one of the following:
•
0x00, 0x08, 0x10, 0x18 (memory data address order 0x00, 0x04, 0x08, 0x0c, ...)
•
0x08, 0x10, 0x18, 0x00
•
0x10, 0x18, 0x00, 0x08
•
0x18, 0x00, 0x08, 0x10
To implement single-beat transfers, the Memory Controller uses DM[3:0] to mask unwanted bytes or words. The Memory Controller supports
all single-beat transfer sizes from 1 to 8 contiguous bytes within a single modulo 8 address range.
all single-beat transfer sizes from 1 to 8 contiguous bytes within a single modulo 8 address range.
A Single transfer is exactly 1 beat on the XLD bus. The relevant data for a Single transfer is always within the first 2 beats on the memory
bus, allowing the command to be aborted (interrupt) as soon as possible.
bus, allowing the command to be aborted (interrupt) as soon as possible.
8.4.4
Commands
When an internal bus master accesses SDRAM address space, the Memory Controller generates the corresponding SDRAM command.
lists SDRAM commands supported by the Memory Controller.
Many commands require a delay before the next command may be issued; sometimes the delay depends on the type of the next command.
These delay requirements are managed by the values programmed in the Memory Controller Configuration registers.
These delay requirements are managed by the values programmed in the Memory Controller Configuration registers.
8.4.4.1
Load Mode/Extended Mode Register Command
The Load Mode Register (LMR) and Load Extended Mode Register (LEMR) commands are used during SDRAM initialization only.
When a bus master writes to the Memory Controller Mode register, the Memory Controller generates the LMR or LEMR command to forward
the data to the memory. In these two operations, data written to the Memory Controller is put on the SDRAM address and bank select busses.
The bank select data selects the Mode or Extended Mode register.
the data to the memory. In these two operations, data written to the Memory Controller is put on the SDRAM address and bank select busses.
The bank select data selects the Mode or Extended Mode register.
The Memory Controller Mode register must be enabled before writing, and disabled after all memory Mode register operations are complete.
This is done by setting or clearing the Control register mode_en bit.See
This is done by setting or clearing the Control register mode_en bit.See
Table 8-4. SDRAM Commands
Function
Symbol
CKE
CS
RAS
CAS
WE
BA[1:0]
A10
Other A
Command Inhibit
INH
H
H
X
X
X
X
X
X
No Operation
NOP
H
L
H
H
H
X
X
X
Read
READ
H
L
H
L
H
V
L
V
Write
WRIT
H
L
H
L
L
V
L
V
Row and Bank Active
ACT
H
L
L
H
H
V
V
V
Burst Terminate
BST
H
L
H
H
L
X
X
X
Precharge All Banks
PALL
H
L
L
H
L
X
H
X
Load Mode Register
LMR
H
L
L
L
L
LL
V
V
Load Extended Mode Register
LEMR
H
L
L
L
L
LH
V
V
CBR Auto Refresh
AREF
H
L
L
L
H
X
X
X
Self Refresh
SREF
H
→L
L
L
L
H
X
X
X
Power Down
PDWN
H
→L
H
X
X
X
X
X
X
Note:
1.
H = High
2.
L = Low
3.
V = Valid
4.
X = Don’t care