Freescale Semiconductor MPC5200B ユーザーズマニュアル
MPC5200B Users Guide, Rev. 1
10-16
Freescale Semiconductor
Registers
10.3.2.2
Target Base Address Translation Register 0 PCITBATR0(RW) —MBAR + 0x0D64
10.3.2.3
Target Base Address Translation Register 1 PCITBATR1(RW) —MBAR + 0x0D68
msb
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
Base Address Translation 0
Reserved
W
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31 lsb
R
Reserved
En
W
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bits
Name
Description
0:13
Base Address
Translation 0
This base address register corresponds to a hit on the BAR0 in MPC5200B PCI Type 0
Configuration space register from PCI space. When there is a hit on MPC5200B PCI
BAR0 (MPC5200B as Target), the upper 14 bits of the external PCI address (256Kbyte
boundary) are written over by this register value to address some space in MPC5200B.
In normal operation, this value should be written during the initialization sequence only
to point to the internal Register space.
Configuration space register from PCI space. When there is a hit on MPC5200B PCI
BAR0 (MPC5200B as Target), the upper 14 bits of the external PCI address (256Kbyte
boundary) are written over by this register value to address some space in MPC5200B.
In normal operation, this value should be written during the initialization sequence only
to point to the internal Register space.
14:30
Reserved
Unused bits. Software should write zero to this register.
31
Enable 0
This bit enables a transaction in BAR0 space. If this bit is zero and a hit on MPC5200B
PCIBAR0 occurs, the target interface gasket will abort the PCI transaction.
PCIBAR0 occurs, the target interface gasket will abort the PCI transaction.
msb 0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
Base Address
Translation 1
Reserved
W
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31 lsb
R
Reserved
En
W
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0