Freescale Semiconductor MPC5200B ユーザーズマニュアル
MPC5200B Users Guide, Rev. 1
10-18
Freescale Semiconductor
Registers
10.3.2.5
Initiator Window 0 Base/Translation Address Register PCIIW0BTAR(RW)—MBAR +
0x0D70
0x0D70
23
Write Combine
Disable
(WCD)
This control bit applies only when MPC5200 is Target. When set, it prevents the PCI
Controller from automatically combining write data to be sent out on the XL bus as a burst,
if possible. Instead, data is transferred as soon as possible on the XL bus as single-beat
transactions.
Controller from automatically combining write data to be sent out on the XL bus as a burst,
if possible. Instead, data is transferred as soon as possible on the XL bus as single-beat
transactions.
Better target write performance is achieved when this bit cleared.
24:31
Write Combine
Timer (WCT)
This register contains the timer value, in PCI clocks, used when a partial burst has been
buffered in the target write data path and write data stops being transferred to local memory
from the external PCI device. Every time a sequential beat of write data is stored in the
buffer, the counter is reset with this value.
buffered in the target write data path and write data stops being transferred to local memory
from the external PCI device. Every time a sequential beat of write data is stored in the
buffer, the counter is reset with this value.
If partial burst data has been buffered, thereby activating the count-down counter, and this
field is reprogrammed to a value less than the current counter value, the counter will jump
down to the new write combine timer value. This way, software can force the write buffer to
flush data to the XL bus more quickly than when the counter was initialized.
field is reprogrammed to a value less than the current counter value, the counter will jump
down to the new write combine timer value. This way, software can force the write buffer to
flush data to the XL bus more quickly than when the counter was initialized.
The reset value of the write combine timer is 0x08. All 8 bits are programmable.
msb 0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
Window 0 Base Address
Window 0 Address Mask
W
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31 lsb
R
Window 0 Translation Address
Reserved
W
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bits
Name
Description
0:7
Window 0 Base
Address
One of three base address registers to determine an XL bus hit on PCI. At most, the upper
byte of the address is decoded. The Window 0 Address Mask register determines what
bits of this register to compare the XL bus address against to generate the hit.
byte of the address is decoded. The Window 0 Address Mask register determines what
bits of this register to compare the XL bus address against to generate the hit.
Note: The smallest possible Window is a 16 MByte block.
8:15
Window 0
Address Mask
The Window 0 Address Mask Register masks the corresponding XL bus base address bit
of the base address for Window 0 (Window 0 Base Address) to instruct the address
decode logic to ignore or “don’t care” the bit. If the base address mask bit is set, the
associated base address bit of Window 0 is ignored when generating the PCI hit. Bit 16
masks bit 24, bit 17 masks bit 25, and so on.
of the base address for Window 0 (Window 0 Base Address) to instruct the address
decode logic to ignore or “don’t care” the bit. If the base address mask bit is set, the
associated base address bit of Window 0 is ignored when generating the PCI hit. Bit 16
masks bit 24, bit 17 masks bit 25, and so on.
0 Corresponding address bit is used in address decode
1 Corresponding address bit is ignored in address decode
For XL Bus accesses to Window 0 address range, this byte also determines which upper
8 bits of the XL Bus address to pass on for presentation as a PCI address. Any address
bit used to decode the XL Bus address, indicated by a “0”, will be translated. This provides
a way to overlay a PCI page address onto the XL Bus address. A “1” in the Address Mask
byte indicates that the XL Bus address bit will be passed to PCI unaltered.
8 bits of the XL Bus address to pass on for presentation as a PCI address. Any address
bit used to decode the XL Bus address, indicated by a “0”, will be translated. This provides
a way to overlay a PCI page address onto the XL Bus address. A “1” in the Address Mask
byte indicates that the XL Bus address bit will be passed to PCI unaltered.