Freescale Semiconductor MPC5200B ユーザーズマニュアル
Registers
MPC5200B Users Guide, Rev. 1
Freescale Semiconductor
10-21
10.3.2.9
Initiator Control Register PCIICR(RW) —MBAR + 0x0D84
8:11
Reserved
Reserved register. Write a zero to this register.
12:15
Window 1Control
[3:0]
Bit[3] - IO/M#.
Bit[2:1] - PRC.
Bit[0] - Enable.
16:19
Reserved
Reserved register. Write a zero to this register.
20:23
Window 0 Control
[3:0]
Bit[3] - IO/M#.
Bit[2:1] - PRC.
Bit[0] - Enable.
24:31
Reserved
Reserved register. Write a zero to this register.
msb
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
Reserved
REE
IAE
TAE
Reserved
W
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31 lsb
R
Reserved
Maximum Retries
W
RESET
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Bits
Name
Description
0:4
Reserved
Unused bits. Software should write zero to this register.
5
Retry Error
Enable
(RE)
This bit enables CPU Interrupt generation in the case of Retry Error termination of a packet
transmission. It may be desirable to mask CPU interrupts, but in such a case, software
should poll the status bits to prevent a possible lock-up condition.
transmission. It may be desirable to mask CPU interrupts, but in such a case, software
should poll the status bits to prevent a possible lock-up condition.
6
Initiator Abort
Enable
(IAE)
This bit enables CPU Interrupt generation in the case of Initiator Abort termination of a
packet transmission. It may be desirable to mask CPU interrupts, but in such a case,
software should poll the status bits to prevent a possible lock-up condition.
packet transmission. It may be desirable to mask CPU interrupts, but in such a case,
software should poll the status bits to prevent a possible lock-up condition.
7
Target Abort
Enable
(TAE)
This bit enables CPU Interrupt generation in the case of Target Abort termination of a packet
transmission. It may be desirable to mask CPU interrupts, but in such a case, software
should poll the status bits to prevent a possible lock-up condition.
transmission. It may be desirable to mask CPU interrupts, but in such a case, software
should poll the status bits to prevent a possible lock-up condition.
8:23
Reserved
Unused bits. Software should write zero to this register.
24:31
Maximum
Retries
This bit field controls the maximum number of automatic PCI retries to permit per
transaction. The retry counter is reset at the beginning of each transaction (i.e. it is not
cumulative). Setting the Maximum Retries to 0x00 allows infinite automatic retry cycles.
transaction. The retry counter is reset at the beginning of each transaction (i.e. it is not
cumulative). Setting the Maximum Retries to 0x00 allows infinite automatic retry cycles.
A finite (0x01 to 0xff) Maximum Retries value will detect the maximum PCI retries and the
next retry will abort the transaction. For a Write transaction an interrupt will be generated,
for a Read transaction an interrupt and a TEA on the XL Bus will be generated.
next retry will abort the transaction. For a Write transaction an interrupt will be generated,
for a Read transaction an interrupt and a TEA on the XL Bus will be generated.