Freescale Semiconductor MPC5200B ユーザーズマニュアル
MPC5200B Users Guide, Rev. 1
12-8
Freescale Semiconductor
Host Control (HC) Operational Registers
12.4.2.3
USB HC Command Status Register—MBAR + 0x1008
HC uses the HC Command Status register to receive (Rx) commands issued by HCD. It reflects the current HC status. To HCD, it appears to
be a write-to-set register. HC ensures bits written as 1 are set in the register, while bits written as 0 remain unchanged in the register. HCD
may issue multiple distinct commands to HC without concern for corrupting previously issued commands. HCD has normal read access to all
bits.
be a write-to-set register. HC ensures bits written as 1 are set in the register, while bits written as 0 remain unchanged in the register. HCD
may issue multiple distinct commands to HC without concern for corrupting previously issued commands. HCD has normal read access to all
bits.
The SchedulingOverrunCount field indicates the number of frames in which HC detects scheduling overrun errors. This occurs when the
Periodic list does not complete before EOF. When a scheduling overrun error is detected, HC increments the counter and sets
SchedulingOverrun field in HcInterruptStatus register.
Periodic list does not complete before EOF. When a scheduling overrun error is detected, HC increments the counter and sets
SchedulingOverrun field in HcInterruptStatus register.
29
PLE
PeriodicListEnable—setting bit enables periodic list processing in next Frame. If cleared by
HCD, periodic list processing does not occur after the next SOF. HC checks this bit prior to
starting list processing.
HCD, periodic list processing does not occur after the next SOF. HC checks this bit prior to
starting list processing.
30:31
CBSR
ControlBulkServiceRatio—field specifies the service ratio between Control and Bulk EDs.
Before processing non-periodic lists, HC compares the ratio specified with its internal count
on how many non-empty Control EDs have been processed, in determining whether to
continue serving another Control ED or switching to Bulk EDs. When crossing the frame
boundary, the internal count is retained. In case of reset, HCD is responsible for restoring
this value.
Before processing non-periodic lists, HC compares the ratio specified with its internal count
on how many non-empty Control EDs have been processed, in determining whether to
continue serving another Control ED or switching to Bulk EDs. When crossing the frame
boundary, the internal count is retained. In case of reset, HCD is responsible for restoring
this value.
CBSR=Number of Control EDs Over Bulk EDs Served
0=1:1
1=2:1
2=3:1
3=4:1
Table 12-3. USB HC Command Status Register
msb 0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
Reserved
SOC
W
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31 lsb
R
Reserved
OCR
BLF
CLF
HCR
W
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bits
Name
Description
0:13
—
Reserved
14:15
SOC
SchedulingOverrunCount—bits are incremented on each scheduling overrun error. SOC is
initialized to 00 and wraps at 11. SOC increments when a scheduling overrun is detected,
even if SchedulingOverrun in HcInterruptStatus has already been set. HCD uses SOC to
monitor any persistent scheduling problems.
initialized to 00 and wraps at 11. SOC increments when a scheduling overrun is detected,
even if SchedulingOverrun in HcInterruptStatus has already been set. HCD uses SOC to
monitor any persistent scheduling problems.
16:27
—
Reserved
28
OCR
OwnershipChangeRequest—OS HCD sets this bit to request an HC change of control.
When set, HC sets the OwnershipChange field in HcInterruptStatus. After changeover, this
bit is cleared and remains clear until the next OS HCD request.
When set, HC sets the OwnershipChange field in HcInterruptStatus. After changeover, this
bit is cleared and remains clear until the next OS HCD request.
Bits
Name
Description