Freescale Semiconductor MPC5200B ユーザーズマニュアル
MPC5200B Users Guide, Rev. 1
12-10
Freescale Semiconductor
Host Control (HC) Operational Registers
12.4.2.5
USB HC Interrupt Enable Register—MBAR + 0x1010
Each enable bit in the HC Interrupt Enable register corresponds to an associated interrupt bit in the HcInterruptStatus register. The
HcInterruptEnable register is used to control which events generate a hardware interrupt. When:
HcInterruptEnable register is used to control which events generate a hardware interrupt. When:
1.
a bit is set in the HcInterruptStatus register, and
2.
the corresponding bit is set in the HcInterruptEnable register, and
3.
the MasterInterruptEnable bit is set, then
4.
a hardware interrupt is requested on the host bus.
Writing 1 to a bit in this register sets the corresponding bit, whereas writing 0 to a bit in this register leaves the corresponding bit unchanged.
On read, the current value of this register is returned.
On read, the current value of this register is returned.
25
RHSC
RootHubStatusChange—bit is set when HcRhStatus content or content of any
HcRhPortStatus[Number of Downstream Port] changes.
HcRhPortStatus[Number of Downstream Port] changes.
26
FNO
FrameNumberOverflow—bit is set when HcFmNumber msb (bit 15) changes value (from 0 to
1, or from 1 to 0) and after HccaFrameNumber is updated.
1, or from 1 to 0) and after HccaFrameNumber is updated.
27
UE
UnrecoverableError—bit is set when HC detects a system error not related to USB. HC should
not proceed with processing or signaling prior to the system error being corrected. HCD clears
this bit after HC is reset.
not proceed with processing or signaling prior to the system error being corrected. HCD clears
this bit after HC is reset.
28
RD
ResumeDetected—bit is set when HC detects a USB device asserting a resume signal. It is
the transition from no resume signaling to resume signaling that causes this bit to be set. This
bit is not set when HCD sets the USBRESUME state.
the transition from no resume signaling to resume signaling that causes this bit to be set. This
bit is not set when HCD sets the USBRESUME state.
29
SF
StartofFrame—bit is set by HC at each start of a frame and after updating the
HccaFrameNumber. HC also generates an SOF token at the same time.
HccaFrameNumber. HC also generates an SOF token at the same time.
30
WDH
WritebackDoneHead—bit is set immediately after HC writes HcDoneHead to
HccaDoneHead. Further HccaDoneHead updates do not occur until this bit is cleared. HCD
should only clear this bit after saving HccaDoneHead contents.
HccaDoneHead. Further HccaDoneHead updates do not occur until this bit is cleared. HCD
should only clear this bit after saving HccaDoneHead contents.
31
SO
SchedulingOverrun—bit is set when USB schedule for the current Frame overruns and after
an HccaFrameNumber update. A scheduling overrun also causes the HcCommandStatus
SOC to increment.
an HccaFrameNumber update. A scheduling overrun also causes the HcCommandStatus
SOC to increment.
Table 12-5. USB HC Interrupt Enable Register
msb 0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
MIE
OC
Reserved
W
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31 lsb
R
Reserved
RHSC
FNO
UE
RD
SF
WDH
SO
W
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bits
Name
Description