Freescale Semiconductor MPC5200B ユーザーズマニュアル
FEC Registers—MBAR + 0x3000
MPC5200B Users Guide, Rev. 1
Freescale Semiconductor
14-19
14.5.9
FEC MIB Control Register—MBAR + 0x3064
The MIB_CONTROL register is a read/write register used to provide control of and to observe the state of the MIB block. This register is
accessed by user software if there is a need to disable the MIB block operation. For example, to clear all MIB counters in RAM the user should
disable the MIB block, clear all MIB RAM locations, then enable the MIB block. The MIB_DISABLE bit is reset to 1.
accessed by user software if there is a need to disable the MIB block operation. For example, to clear all MIB counters in RAM the user should
disable the MIB block, clear all MIB RAM locations, then enable the MIB block. The MIB_DISABLE bit is reset to 1.
Bits
Name
Description
0:23
—
Reserved
24
DIS_PREAMBLE
Asserting this bit causes preamble (32 1s) to not be prepended to the MII
management frame. The MII standard allows the preamble to be dropped, if not
required by the attached PHY device(s).
management frame. The MII standard allows the preamble to be dropped, if not
required by the attached PHY device(s).
25:30
MII_SPEED
Controls the frequency of the MII management interface clock (MDC) relative to
ipb_clk. A 0 value in this field “turns off” the MDC and leaves it in low voltage state.
Any non-zero value results in the MDC frequency of
ipb_clk. A 0 value in this field “turns off” the MDC and leaves it in low voltage state.
Any non-zero value results in the MDC frequency of
1/(MII_SPEED*2) of the ipb_clk frequency.
The MII_SPEED field must be programmed with a value to provide an MDC frequency
of less than or equal to 2.5 MHz to be compliant with the IEEE MII characteristic. The
MII_SPEED must be set to a non-zero value in order to source a read or write
management frame. After the management frame is complete, the MII_SPEED
register may optionally be set to 0 to turn off the MDC. The MDC generated has a 50%
duty cycle except when MII_SPEED is changed during operation (change takes affect
following either a rising or falling edge of MDC).
of less than or equal to 2.5 MHz to be compliant with the IEEE MII characteristic. The
MII_SPEED must be set to a non-zero value in order to source a read or write
management frame. After the management frame is complete, the MII_SPEED
register may optionally be set to 0 to turn off the MDC. The MDC generated has a 50%
duty cycle except when MII_SPEED is changed during operation (change takes affect
following either a rising or falling edge of MDC).
If the ipb_clk is 25MHz, programming MII_SPEED field to 0x5 results in a MDC
frequency of 25MHz * 1/(5*2) = 2.5 MHz.
frequency of 25MHz * 1/(5*2) = 2.5 MHz.
values as a function of the ipb_clk frequency.
31
—
Reserved
Table 14-17. Programming Examples for MII_SPEED Register
ipb_clk Frequency
MII_SPEED (Field in Register)
MDC Frequency
25MHz
$5
2.5MHz
33MHz
$7
2.36MHz
40MHz
$8
2.5MHz
50MHz
$A
2.5MHz
Table 14-18. FEC MIB Control Register
msb 0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
MIB
_
DISAB
L
E
MIB_IDLE
Reserved
W
RESET: 1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31 lsb
R
Reserved
W
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0