Freescale Semiconductor MPC5200B ユーザーズマニュアル
FEC Registers—MBAR + 0x3000
MPC5200B Users Guide, Rev. 1
Freescale Semiconductor
14-21
14.5.11
FEC Hash Register—MBAR + 0x3088
The read-only R_HASH register provides address recognition information from the Rx block about the frame currently being received. These
bits provide information used in the address recognition subroutine.
bits provide information used in the address recognition subroutine.
14.5.12
FEC Tx Control Register—MBAR + 0x30C4
This X_CNTRL register is read/write and is written to configure the transmit block. This register is cleared at system reset. Bits 29:30 should
be modified only when ETHER_EN = 0.
be modified only when ETHER_EN = 0.
30
DRT
Disable Receive on Transmit
0 = Rx path operates independently of Tx
(use for full-duplex or to monitor Tx activity in half-duplex mode).
1 = Disable frames reception while transmitting
(normally used for half-duplex mode).
31
LOOP
Internal Loopback—If set, transmitted frames are looped back internal to the device and
transmit output signals are not asserted. The system clock is substituted for TX_CLK when
LOOP is asserted. DRT must be set to 0 when asserting LOOP.
transmit output signals are not asserted. The system clock is substituted for TX_CLK when
LOOP is asserted. DRT must be set to 0 when asserting LOOP.
Table 14-20. FEC Hash Register
msb 0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
FC
E_D
C
MUL
T
I
CAST
HASH
Reserved
W
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31 lsb
R
Reserved
W
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bits
Name
Description
0
FCE_DC
This is a read-only view of the R_CNTRL register FCE bit.
1
MULTICAST
Set if current Rx frame contained a multi-cast destination address, indicating DA LSB was
set. Cleared if current Rx frame does not correspond to a multi-cast address.
set. Cleared if current Rx frame does not correspond to a multi-cast address.
2:7
HASH
Corresponds to “hash” value of current Rx frame’s destination address. Hash value is a
6-bit field extracted from least significant portion of CRC register.
6-bit field extracted from least significant portion of CRC register.
8:31
—
Reserved
Table 14-21. FEC Tx Control Register
msb 0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
Reserved
W
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bits
Name
Description