Freescale Semiconductor MPC5200B ユーザーズマニュアル
MPC5200B Users Guide, Rev. 1
14-22
Freescale Semiconductor
FEC Registers—MBAR + 0x3000
14.5.13
FEC Physical Address Low Register—MBAR + 0x30E4
The PADDR1 register is written by the user. This register contains the lower 32bits (Bytes 0,1,2,3) of the 48-bit address used in the address
recognition process to compare with the destination address (DA) field of receive frames with an individual DA. In addition, this register is
used in Bytes0:3 of the 6-Byte source address field when transmitting PAUSE frames. This register is not reset and must be initialized.
recognition process to compare with the destination address (DA) field of receive frames with an individual DA. In addition, this register is
used in Bytes0:3 of the 6-Byte source address field when transmitting PAUSE frames. This register is not reset and must be initialized.
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31 lsb
R
Reserved
RFC
_
P
A
USE
TF
C_P
A
USE
FDEN HBC
GTS
W
RESET: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bits
Name
Description
0:26
—
Reserved
27
RFC_PAUSE
This read-only status bit is asserted when a full-duplex flow control pause frame is
received. The transmitter is paused for the duration defined in this pause frame. Bit
automatically clears when the pause duration is complete.
received. The transmitter is paused for the duration defined in this pause frame. Bit
automatically clears when the pause duration is complete.
28
TFC_PAUSE
Assert to transmit a PAUSE frame. When this bit is set, the MAC stops transmission of
data frames after the current transmission is complete. At this time, the INTR_EVENT
register GRA interrupt is asserted. With transmission of data frames stopped, the MAC
transmits a MAC Control PAUSE frame. Next, the MAC clears the TFC_PAUSE bit and
resumes transmitting data frames.
data frames after the current transmission is complete. At this time, the INTR_EVENT
register GRA interrupt is asserted. With transmission of data frames stopped, the MAC
transmits a MAC Control PAUSE frame. Next, the MAC clears the TFC_PAUSE bit and
resumes transmitting data frames.
Note: If the transmitter is paused due to user assertion of GTS or reception of a PAUSE
frame, MAC may still transmit a MAC Control PAUSE frame.
frame, MAC may still transmit a MAC Control PAUSE frame.
29
FDEN
Full Duplex Enable—If set, frames are transmitted independent of Carrier Sense and
Collision inputs.
Collision inputs.
This bit should only be modified when ETHER_EN is deasserted.
30
HBC
Heartbeat Control—If set, the heartbeat check is done following End Of Transmission
(EOT) and the Event Status Register HB bit is set if the collision input does not assert
within the heartbeat window.
(EOT) and the Event Status Register HB bit is set if the collision input does not assert
within the heartbeat window.
This bit should only be modified when ETHER_EN is deasserted.
31
GTS
Graceful Transmit Stop—When this bit is set, the MAC stops transmission after any frame
that is currently being transmitted is complete and the INTR_EVENT register GRA
interrupt is asserted.
that is currently being transmitted is complete and the INTR_EVENT register GRA
interrupt is asserted.
If frame transmission is not currently underway, the GRA interrupt is immediately
asserted. Once transmission completes, a “restart” can be done by clearing the GTS bit.
The next frame in the transmit FIFO is then transmitted.
asserted. Once transmission completes, a “restart” can be done by clearing the GTS bit.
The next frame in the transmit FIFO is then transmitted.
If an early collision occurs during transmission when GTS = 1, transmission stops after
the collision. The frame is transmitted again once GTS is cleared.
the collision. The frame is transmitted again once GTS is cleared.
Note: Old frames may exist in the transmit FIFO and be transmitted when GTS is
reasserted. To avoid this, deassert ETHER_EN after the GRA interrupt.
reasserted. To avoid this, deassert ETHER_EN after the GRA interrupt.
Table 14-22. FEC Physical Address Low Register
msb 0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
PADDR1
W
RESET:
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X