Freescale Semiconductor MPC5200B ユーザーズマニュアル
MPC5200B Users Guide, Rev. 1
15-2
Freescale Semiconductor
Overview
15.1.1
PSC Functions Overview
The PSC module of the MPC5200 provide different groups of interfaces to connect the MPC5200 to other devices.
shows the
groups of interfaces:
Figure 15-1. PSC Functions Overview
1.
PSC Codec Mode: In this section the name Codec mode is used as a collective term for the “normal soft Modem” the SPI, I2S and
ESAI mode. This interfaces are provide by one internal block of the PSC. The interface consist of serial TX and RX lines, a bit
clock line and a FrameSync signal. For these modes the clock configuration is similar and use the same configuration registers.
The transmitter converts the parallel data from the CPU to a serial bit-stream, the receiver converts the serial data from the RX line
to parallel data. The PSCs support Codec mode with 8, 16, 24 and 32 bit data width, with active high or active low FrameSync
signal and with programmable bit clock polarity. All Codec modes can work as an Codec master (PSC dive the bit clock and
FrameSync signals) or as a Codec Slave (PSC receive the bit clock and frame sync signal). For more information about the Codec
mode see
ESAI mode. This interfaces are provide by one internal block of the PSC. The interface consist of serial TX and RX lines, a bit
clock line and a FrameSync signal. For these modes the clock configuration is similar and use the same configuration registers.
The transmitter converts the parallel data from the CPU to a serial bit-stream, the receiver converts the serial data from the RX line
to parallel data. The PSCs support Codec mode with 8, 16, 24 and 32 bit data width, with active high or active low FrameSync
signal and with programmable bit clock polarity. All Codec modes can work as an Codec master (PSC dive the bit clock and
FrameSync signals) or as a Codec Slave (PSC receive the bit clock and frame sync signal). For more information about the Codec
mode see
2.
AC97 Mode: When programmed as AC97 the PSC works as an AC97 Controller, it’s means that the PSC receive the BitClk from
the external AC97 Codec and provide the FrameSync signal to the external Codec. Only PSC1 and 2 support the AC97
functionality. In the normal AC97 mode, the data words for all AC97 slots must be in the TX FIFO including the slot 0,1 and slot
2data. The PSC is not able to modify the control slot data. Also all data words from the RX line will be in the FIFO. Only if the
the external AC97 Codec and provide the FrameSync signal to the external Codec. Only PSC1 and 2 support the AC97
functionality. In the normal AC97 mode, the data words for all AC97 slots must be in the TX FIFO including the slot 0,1 and slot
2data. The PSC is not able to modify the control slot data. Also all data words from the RX line will be in the FIFO. Only if the
Serial
Interrupt
Control Logic
Control lines
RxD
TxD
TxD
Internal Channel
Control Logic
Programmable
Tx/Rx Clock
Communications
Channel
Generation
System Integration
Unit (SIU)
Interrupt Controller
Internal Clock
Source
FIFO System
External Clock
Source
PSC
Internal C-/ IP
Bus System
PSC
Codec
“Soft
Modem”
SPI I2S
AC97
UART
SIR
MIR
FIR
IrDA
ESAI