Freescale Semiconductor MPC5200B ユーザーズマニュアル
MPC5200B Users Guide, Rev. 1
15-38
Freescale Semiconductor
PSC Registers—MBAR + 0x2000, 0x2200, 0x2400, 0x2600, 0x2800, 0x2C00
15.2.28
Rx FIFO Number of Data (0x58)
—
RFNUM
15.2.29
Tx FIFO Number of Data (0x5C)
—
TFNUM
15.2.30
Rx FIFO Data (0x60)
—
RFDATA
Read - write register to access the internal RX FIFO Data register. Reads from this register reads out the receive data. In addition the register
provides the possibility to fill the RX FIFO for debug issues. For more informations about the data format see
provides the possibility to fill the RX FIFO for debug issues. For more informations about the data format see
15.2.31
Rx FIFO Status (0x64)—RFSTAT
For additional informations about the FIFO related status bits see
NOTE
To make sure that the PSC never lost the data in the FIFO, the PSC controller avoid writing to a full
FIFO or reading from an empty FIFO. Therefore the status bits in the FIFO STAT register never
reports an ERROR, UF or OF state. The
FIFO or reading from an empty FIFO. Therefore the status bits in the FIFO STAT register never
reports an ERROR, UF or OF state. The
register reports these errors.
Table 15-57. RX FIFO Number of DATA (0x58)
msb 0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15 lsb
R
Reserved
COUNT[0:8]
W
Reserved
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
Name
Description
0:6
—
Reserved
7:15
COUNT
Number of data bytes in the Rx FIFO.
Table 15-58. Tx FIFO Number of Data (0x5C)
msb 0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15 lsb
R
Reserved
COUNT[0:8]
W
Reserved
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
Name
Description
0:6
—
Reserved
7:15
COUNT
Number of data bytes in the Tx FIFO.
Table 15-59. Rx FIFO Status (0x64)
msb 0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15 lsb
R
Reserved
F
rame[
3
]
F
rame[
2
]
F
rame[
1
]
F
rame[
0
]
Rese
rved
Error
UF
OF
FR
FULL
ALA
R
M
EMP
T
Y
W
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0