Freescale Semiconductor MPC5200B ユーザーズマニュアル

15-56

Freescale Semiconductor

The transmission protocol for the “Cell Phone” mode is the same like in the “Soft Modem” mode. The PSC use the configure and clock 
generation registers is the same as described in the section before, see 

The goal for this mode is, that PSC2, 3 or 6 can generate a BitClk which is synchronous to in the BitClk input on PSC1. Only the 

internal clock distribution is different to the “Soft Modem” mode. The major deviation is, that the “Cell Phone” slave PSCs use the clock from 
PSC1 for BitClk and FrameSync generation instead of Mclk from the CDM module.

PSC1 is the only PSC that can work as “Cell Phone” master, PSC2, 3 or 6 are available as “Cell Phone” slave. The “Cell Phone” master PSC 
must be configured as codec slave, this means that the PSC1 receive the BitClk from the outside. Therefore the 

[GenClk] bit must be 

cleared. The “Cell Phone” slave PSCs must be configured as codec master. Therefore the 

[GenClk] must be set and the FrameSyncDiv 

and BitClkDiv values in the 

register must be set to the desired value, like described in 

. To enable the “Cell Phone” slave functionality the 

[CellSlave] bit must set. If this bit was set the PSCs use the BitClk from 

PSC1 for the internal clock generation instead of the Mclk. If the 

[CellSlave] and the 

[Cell2xClk] bit was set, then the “Cell Phone” 

salve PSCs use the BitClk from PSC1 multiplied by 2 for the internal clock generation. These facts are described in 

shows an example how to configure the PSC system as follows: 

•

PSC1 is “Cell Phone” master, PSC2 works as “Cell Phone” slave

•

both PSC work with 24bit data

•

Data are sampled on the falling edge of BitClk

•

FrameSync is high true

•

MSB first, transfer starts on the leading edge of FrameSync

•

PSC2 us the BitClk from PSC1 multiplied by 2 for clock generation

•

FrameSync every 24BitClk, for both PSCs

•

set FrameSync width to 1 BitClk

•

set the 

TFALARM

 level to 0x010, alarm occurs if 16 byte are in the TxFIFO

•

set the 

 level to 0x00C, alarm occurs if 12 byte space in the RxFIFO

•

enable TxRDY interrupt

BitClk

Frame

PSC 1

BitClk

Frame

PSC 2,3 or 6

Clock

multiply by 2

Mclk (not used)

Clock
Gener-

ation

PSC1 configured as slave

—

receive BitClk and Frame, 

but called “cell phone master”

—

provide clock to 

PSC2, 3 or 6. 

[GenClk] = 0, slave mode

PSC2, 3 or 6 configured as master, provide BitClk and 
Frame, but called “cell phone slave”, receive clock 
from PSC1.

[GenClk] = 1, master mode

[CellSlave] = 1, use clock from PSC1 (normal or 

double clock)

[Cell2xClk] = 0, use normal clock

[Cell2xClk] = 1, use double clock