Freescale Semiconductor MPC5200B ユーザーズマニュアル

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PSC Operation Modes
MPC5200B Users Guide, Rev. 1
Freescale Semiconductor
15-57
15.3.2.6
Transmitting and Receiving in I2S Master Mode
The next support mode is the I2S mode. The I2S transmission is similar to the “Soft Modem” mode. Therefore the configuration is the same 
like described in 
The different is, that during the I2S word 
transmission the FrameSync signal (LRCK) is stable for the complete data word and is the opposite for the next one. To enable the I2S mode 
the 
[I2S] bit must be set. The 
[SyncPol] bit define if the frame starts with a low LRCK signal or with a high LRCK signal. If the 
transmitter detect the start condition he starts to send the data from the TxFIFO. If the receiver detects an start condition, he starts to write the 
data from the RX line to the RxFIFO. The FIFO doesn’t provide the ability to mark the data in the FIFO, therefore only the order in the FIFO 
define if the data was receive/transmit during high or low phase of the LRCK. 
shows the I2S transmission diagram.
Table 15-82. 24-Bit Cell Phone Master Mode for PSC1
Register
Value
Setting
0x0A
Disable the Tx and Rx part for configuration if the PSC was enabled by the work 
before.
0x07100000
Select the 24bit Codec mode, msb first, DTS1 = 0, slave mode
0x000C
set the RFALARM level to 0x00C
TFALARM
0x0010
set the TFALARM level to 0x010
0x0100
enable TxRDY interrupt
Port_Config
0x00000066
Select the Pin-Muxing for PSC1,PSC2 Codec mode, see 
0x05
Enable Tx and Rx
Table 15-83. 24-Bit Cell Phone Slave Mode for PSC2
Register
Value
Setting
0x0A
Disable the Tx and Rx part for configuration if the PSC was enabled by the work 
before.
0x07980000
Select the 24bit Codec mode, msb first, DTS1 = 0, master mode, cell phone 
master
0x01170000
select the BitClk and Frame frequency
0x00
select the FrameSync width, default value
0x000C
set the RFALARM level to 0x00C
TFALARM
0x0010
set the TFALARM level to 0x010
0x0100
enable TxRDY interrupt
Port_Config
0x00000066
Select the Pin-Muxing for PSC12, PSC2 Codec mode, see 
0x05
Enable Tx and Rx