Freescale Semiconductor MPC5200B ユーザーズマニュアル

Freescale Semiconductor

15-59

An other available Codec mode is the SPI mode. The PSC support a full duplex SPI interface. This mode is chosen by setting 

[SPI] = 1, 

which must be true in order for the MSTR, CPOL, CPHA and UseEOF bits in the 

 register to take effect. In SPI mode, the 

[SIM] 

bits must also be set to select the data width. To configure the PSC to act like an SPI master set 

[MSTR] = 1, or set 

[MSTR] = 0 to 

configure the PSC as an SPI slave. When 

[MSTR] bit was set then 

[GenClk] must also be set to 1 since the PSC is driving the SPI 

clock line. When 

[MSTR] = 0 then 

[GenClk] must be set to 0 since the external SPI is driving the SCK clock line. The CPOL and 

CPHA bits in the 

 register operate exactly the same way as they do in an SPI, and their values must be the same as the CPOL and CPHA 

bits in the SPI device that is communicating with the PSC. The 

[UseEOF] bit has an effect only when 

[MSTR] = 1 for master mode. 

If the UseEOF bit is cleared then only one data word (8, 16, 24 or 32 bit width depend on the 

[SIM] filed) will be send before Slave 

Select (SS) goes high/inactive. When 

[UseEOF] = 1then the number of bytes transferred prior to SS going high is controlled by the 

BestComm task that fills the Tx FIFO. By using the "tfdOnExit" keyword in the for-loop that fills the Tx FIFO, the last byte written into the 
Tx FIFO by the for-loop is marked with an EOF flag. As the PSC reads bytes out of the Tx FIFO it will hold SS low/active until it transmits 
a byte whose EOF flag is set. In this mode there is virtually no limit on how many bytes can be sent in one SPI transfer.

To mark a data word with the EOF flag during a IPB transfer set the Bit 

[NXTEOF] before writing the last data word to the TX FIFO. 

This bit will be cleared after the next write access to the TX FIFO.

The 

[SHDIR] bit controls the shift direction in SPI mode, just as it does in the non-SPI Codec modes. The DTS1, MultiWd, ClkPol, 

SyncPol, CellSlave and Cell2xClk bits in the 

 register have no effect in SPI mode. 

In SPI master mode the BitClk (SCK) frequency is generated by dividing down the Mclk frequency, see 

. Additional to the BitClk generation the DSCLK delay and the DTL delay must be defined. The DSCLK defines the 

delay between the SS going active and the first BitClk (SCK) clock pulse transition. The DSCLK delay is created by dividing down the Mclk 
frequency. The delay between consecutive transfers is created by dividing down the IPB clock frequency. For more informations about the 
delay generation see also the description of the 

,

and

register

.

In SPI master mode the PSC controls the serial data transfers. In this mode if either the Tx FIFO becomes empty (underrun) or the Rx FIFO 
becomes full (overflow) in the middle of a multi-byte transfer, rather than set the Tx underrun or Rx overflow status bits the PSC will keep 
the Slave Select signal low/active and stop the SCK serial clock. When the Tx FIFO doesn’t become empty and the Rx FIFO becomes not full 
the transfer proceeds.

In SPI slave mode the Mclk must be running/enabled even though it is not being used to generate the serial clock SCK, which is provided by 
the external master SPI device. The frequency of Mclk is not critical, as long as it is faster than the SCK frequency.

       DSCKL delay =

Mclk

CCR[0:7] +1

DTL =

IPB clock frequency

 CT[0:15] +2 

where:

CT[0:15] = {

[0:7], 

[0:7]}

+ 

3

Mclk frequency